Datasheet

Electrical Characteristics
17-18 MCF5206e USER’S MANUAL MOTOROLA
17.3.12.2 OUTPUT TIMING SPECIFICATIONS BETWEEN SCL AND SDA.
Table 17-12. Output Timing Specifications Between SCL and SDA
1
Note: Units for these specifications are in processor CLK units.
2
Note: Output numbers are dependent on the value programmed into the MFDR; an MFDR programmed with the maximum
frequency (MFDR = 0x20) will result in minimum output timings as shown in the above table. The MBUS interface is designed to
scale the actual data transition time to move it to the middle of the SCL low period. The actual position is affected by the prescale and
division values programmed into the MFDR; however, numbers given in the above table are the minimum values.
3
Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time required for SCL or
SDA to reach a high level depends on external signal capacitance and pull-up resistor values.
4
Specified at a nominal 50pF load.
17.3.12.3 TIMING SPECIFICATIONS BETWEEN CLK AND SCL, SDA.
Table 17-13. Timing Specifications Between CLK and SCL, SDA
1
Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this specification applies only
when SCL or SDA are driven low by the processor. The time required for SCL or SDA to reach a high level depends on external signal
capacitance and pull-up resistor values.
2
Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this specification applies only
when SCL or SDA are actively being driven or held low by the processor.
NAME CHARACTERISTIC
40 MHz 54 MHz
UNIT
MIN MAX MIN MAX
M1
1,2
Start condition hold time 6 — 6 — CLKs
M2
1,2
Clock low period 10 — 10 — CLKs
M3
3
SCL/SDA rise time (from V
l
= 0.5V to V
h
= 2.4V)
————us
M4
1,2
Data hold time 7 — 7 — CLKs
M5
4
SCL/SDA fall time (from V
h
= 2.4V to V
l
= 0.5V)
— TBD — TBD us
M6
1,2
Clock high time 10 — 10 — CLKs
M7
1,2
Data setup time 2 — 2 — CLKs
M8
1,2
Start condition setup time (for repeated start
condition only)
20 — 20 — CLKs
M9
1,2
Stop condition setup time 10 — 10 — CLKs
NAME CHARACTERISTIC
40 MHz 54 MHz
UNIT
MIN MAX MIN MAX
M10 SCL, SDA Valid to CLK (Setup) 5.5 — 4 — ns
M11 CLK to SCL, SDA Invalid (Hold) 4.5 — 4.5 — ns
M12
1
CLK to SCL, SDA Valid Low 3 18.5 3 14 ns
M13
2
CLK to SCL, SDA Invalid (Output Hold) 3 — 3 — ns
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...