Datasheet

Electrical Characteristics
MOTOROLA MCF5206e USER’S MANUAL 17-21
17.3.16 DMA Controller AC Timing Specifications
Table 17-15. DMA Controller AC Timing
17.3.17 DMA Controller Timing Diagram
Figure 17-15. DMA Timing
17.3.18 IEEE 1149.1 (JTAG) AC Timing Specifications
Table 17-16. IEEE 1149.1 (JTAG) AC Timing Specifications
NAME
CHARACTERISTIC
40 MHz 54 MHz
UNIT
MIN MAX MIN MAX
D1 DREQ
Valid to CLK (Setup) 4 — 2.5 — ns
D2 CLK to DREQ
Invalid (Hold) 4.5 — 4.5 — ns
NAME CHARACTERISTIC
40 MHz 54 MHz
UNIT
MIN MAX MIN MAX
— TCK frequency of operation 0 10 0 10 MHz
J1 TCK cycle time 100 — 100 — ns
J2a TCK clock pulse high width measured at 1.5V 40 — 40 — ns
J2b TCK clock pulse low width measured at 1.5V 40 — 40 — ns
J3a
TCK fall time (from V
h
= 2.4V to V
l
= 0.5V)
—5—5ns
J3b
TCK rise time (from V
l
= 0.5V to V
h
= 2.4V)
—5—5ns
J4 TDI, TMS to TCK rising (Setup) 10 — 10 — ns
J5 TCK rising edge to TDI, TMS Invalid (Hold) 15 — 15 — ns
J6 Boundary scan data valid to TCK rising edge (Setup) 10 — 10 — ns
J7 Boundary scan data invalid to TCK rising edge (Hold) 15 — 15 — ns
J8 TRST
pulse width (asynchronous to clock edges) 15 — 15 — ns
J9
TCK falling edge to TDO valid
(signal from driven or three-state)
— 30 — 30 ns
J10 TCK falling edge to TDO high impedance — 30 — 30 ns
J11
TCK falling edge to boundary scan data valid
(signal from driven or three-state)
— 35 — 35 ns
J12
TCK falling edge to boundary scan data high
impedance
— 35 — 35 ns
CLK
D1
D2
DREQ IN
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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