Datasheet

Introduction
MOTOROLA MCF5206e USER’S MANUAL 1-15
1.3.2 MAC Module
The MAC unit provides a common set of simple DSP operations and speeds the execution
of the integer multiply instructions in the ColdFire core. It provides functionality in three
related areas: faster multiplications of signed and unsigned operands; and new
miscellaneous register operations. Multiplies of 16x16 and 32x32 with 32-bit accumulates
are supported. The MAC has a single clock issue for 16x16 multiplies and implements a 3-
stage execution pipeline.
1.3.3 Hardware Divide Module
The MCF5206e processor includes a hardware divider which performs a number of interger
divide operations. The supported divide functions include: 32/16 producing a 16-bit quotient
and 16-bit remainder, 32/32 producing a 32-bit quotient, and 32/32 producing a 32-bit
remainder.
The hardware divide function provides enhanced functionality, particularly in printing
applications. With graphics-based printing this has resulted in as much as 15 percent
performance improvement.
1.3.4 Instruction Cache
The instruction cache improves system performance by providing cached instructions to the
execution unit in a single clock. The MCF5206e processor uses a 4K-byte, direct-mapped
instruction cache to achieve 50 MIPS at 54MHz. The cache is accessed by physical
addresses, where each 16-byte line consists of an address tag and a valid bit.
The instruction cache also includes a bursting interface for 32 bit, 16 bit, and 8 bit port sizes
to quickly fill cache lines.
1.3.5 Internal SRAM
The 8 KByte on-chip SRAM provides one clock-cycle access for the ColdFire core. This
SRAM can store processor stack and critical code or data segments to maximize
performance.
SUBX Dy,Dx 32 Destination – Source – X → Destination
SWAP Dx 16 MSW of Dx ←→ LSW of Dx
TRAP none none SP – 4 → SP;PC → (SP);
SP – 2 → SP;SR → (SP);
SP – 2 → SP; Format → (SP);
Vector Address → PC
TRAPF none
#<data>
none
16
32
PC + 2 → PC
PC + 4 → PC
PC + 6 → PC
TST <ea>y 8,16,32 Set Condition Codes
UNLK Ax 32 Ax →SP; (SP) → Ax; SP + 4 → SP
WDDATA <ea>y 8,16,32 <ea>y →DDATA port
WDEBUG <ea>y 2 x 32 <ea>y → Debug Module
INSTRUCTION OPERAND SYNTAX OPERAND SIZE OPERATION
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Freescale Semiconductor, Inc.
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