Datasheet

MOTOROLA MCF5206e User’s Manual Index-1
INDEX
A
AABR 15-32, 15-33
AATR 15-28
ABLR/ABHR 15-28
Access Control Registers 4-8
access error 1-6, 8-3
on operand writes 3-9
Access Fault Exception 8-2, 9-39
Access Type and Mode (ATM) 6-3
ACR0, ACR1 4-3, 4-8
Address / Data (A/D) Field 15-10
Address Attribute Breakpoint Register (AATR) 15-
13, 15-15, 15-30
address bus 2-3, 2-4
address error 1-6
Address Error Exception 3-9
address hold 9-8, 9-34
Address masking 9-5
Address Multiplexing 11-8
address multiplexing for external master transfers
11-41
address setup 9-8, 9-11, 9-34
address setup and hold features 9-22
Address Space Masks 8-8
Addressing Modes
index sizing and scaling 1-10
program counter indirect 1-10
register indirect 1-10
aligned and misaligned operand references 15-33
aligned transfers 6-67
alignment 6-48
alternate master transfers 2-9, 6-68, 11-41
Arbitration 13-8,13-10
arbitration states 6-66
Asynchronous Acknowledge 6-29, 6-34
Asynchronous Transfer Acknowledge (ATA) 2-10, 6-
4, 6-30, 6-47, 6-52
ATM 2-9
Automatic Echo 12-19
autovector 8-4, 8-5, 8-6, 8-10
autovectored interrupt 8-4
Autovectoring 3-10, 6-49
B
Bank Page Size 11-61
Base Address 11-58
Base Address Mask 11-59
Baud-Rate Generator 12-5
BDM command 15-29
BDM Command Set Summary 15-8
BDM connector 15-38
BDM Serial Interface 15-6
Bits per Character 12-19
BKPT 2-18, 15-36
BKPT input pin 15-5
block mode 12-11, 12-18
break condition 12-9
Breakpoint Registers 15-28, 15-30
breakpoint response (table 16-8) 15-26
Breakpoint Status 15-35
burst page mode 11-32, 11-47, 11-53, 11-54, 11-57
burst transfer
fast page mode 11-21
normal mode 11-18
burst transfers 4-7, 6-9, 6-16, 6-74, 9-7, 9-22, 11-44
burst transfers and chip selects 9-13
bursting 6-9
burst-inhibited transfer 6-22, 6-16, 6-62
Burst-Inhibited Write Transfer 6-26
bus arbitration 2-11, 11-30
operation, 6-54
protocol, 6-54, 6-61
Bus Driven (BD) 2-12
bus error 6-52, 7-11
Bus Grant (BG) 2-11
bus interface 6-1
bus lock 8-9
bus lock bit 2-11
bus monitor 8-2, 8-15
Bus Request (BR) 2-11
Bus Sizing 6-7, 9-7
Bus Timeout Monitor 8-9, 8-13
BYPASS Instruction 16-5
C
Cache Coherency 4-3
Cache Control Register 4-6
Cache Freeze 4-7
Cache Invalidate 4-3, 4-7
cache line filling 6-16
Cache Miss Fetch Algorithm 4-4
CACR 4-3, 4-6
calling address 13-3, 13-10
calling master 13-4
Capture Edge 14-4
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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