Datasheet

Index
Index-2 MCF5206e User’s Manual MOTOROLA
Capture Event 14-6
Capture Mode 14-3
CAS and RAS 11-57
CAS Precharge Time 11-57
CAS timing 11-3
CCR 3-3
change-of-flow operations 15-2
changing receiver configuration 12-25
Channel prioritization 7-14
character mode 12-11 , 12-18
Chip Select Address Register (CSAR0-CSAR7) 9-28
chip selects 1-17, 2-4, 2-5, 9-5, 9-7
Chip-Select Control Register (CSCR0 -7) 9-31
Chip-Select Control Register 0 (CSCR0) 6-85 , 9-8
Chip-Select Mask Register (CSMR0-CSMR7) 9-29
chip-selects 8-16 , 9-1
access permission 9-6
alernate master operation, 9-20
description 2-4
programming model, 9-26
CLAMP Instruction 16-5
clear-to-send operation 12-6
CLK 2-12
ColdFire BDM Commands 15-9
Column Address Strobe Time 11-56
Column Address Strobes 2-13
Command
format 15-12
Sequence Diagram 15-11
Concurrent BDM and Processor Operation 15-28
Condition Code Register 3-3
Configuration/Status Register (CSR) 15-35
Continuous Mode 7-12
Control Register Map 15-22
CPU Halt 15-4
CPU privilege level 15-37
CTS 12-28
Cycle Steal 7-12
D
Data
Registers 15-13 , 15-25
Data Breakpoint Register (DBR, DBMR) 15-32
data bus 2-4 , 6-2
data formats 1-10
Data Registers 3-2
data transfer
alternate master 6-68
asynchronous-acknowledge 6-29, 6-32
bursting read 6-34
bursting word-read, 6-16 , 6-18
bursting write 6-19, 6-37
burst-inhibited read, 6-22 , 6-41
burst-inhibited write 6-44
longword-read 6-12
longword-write 9-9
operation, 6-6
word-write 6-15
DBR/DBMR 15-28
DDATA pins 15-2
Debug Control Registers (DRc) 15-29
Debug Data 2-17
Debug Interrupt 3-10
Debug mode 16-2, 16-8
debug module 2-17
BDM connector 15-38
command set 15-7
emulator mode 15-27
hardware reuse 15-28
interrupt 15-26
processor status 15-2
programming model 15-29
real-time debug 15-26
registers
address attribute breakpoint (AABR) 15-32 ,
15-33
serial interface 15-6
signals 2-16
theory of operation 15-26
Debug Programming Model 15-29
Debug Support
real-time debug support
theory of operation 15-26
debug module hardware 15-28
reuse of debug module hardware (Rev. A)
15-28
shared BDM/breakpoint hardware (table
16-9) 15-28
emulator mode 15-27
Default Memory 9-5, 9-38, 9-41
Default Memory Control Register (DMCR) 9-38
Definition of DRc Encoding - Write 15-25
Development Serial Clock 2-17
Development Serial Input 2-18
Development Serial Output 2-18
Differences Between ColdFire and CPU32 BDM
15-38
Disable command 12-6
Disabling IEEE 1149.1 Standard Operation 16-8
DMA
Channel
Initialization 7-14
Programming Sequence 7-14
DMA acknowledge 7-16
DMA channels 1-16
DMA Module 2-15
DMA Request 2-15, 7-3
Double Bus Fault 6-5
DRAM 6-4 , 6-5 , 6-16 , 6-22 , 11-58 , 11-59 , 11-60
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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