Datasheet

Index
MOTOROLA MCF5206e User’s Manual Index-7
three-wire mode 6-61
Timer
Programming Model 14-3
timer 2-15 , 12-3
interrupts 8-5
Timer Capture Register (TCR) 14-5
Timer Counter (TCN) 14-5
Timer Event Regiser (TER) 14-6
Timer Input 2-15
timer interrupts 8-5
Timer Mode Register (TMR) 14-4
timer module 1-16 , 14-1
block diagram 14-2
Timer Output 2-15
Timer Reference Register (TRR) 14-5
TIN 14-3
TMS 16-3
Trace Exception 3-9
Transfer Acknowledge (TA) 2-10, 6-4
transfer data size 2-9
Transfer Error Acknowledge (TEA) 2-11, 6-52
transfer mask bit 9-30
Transfer Start (TS) 2-10, 6-2
Transfer type encodings 2-9
Transmit Acknowledge 13-9
Transmit Data 2-15
transmit mode 13-12
Transmit/Receive mode 13-8, 13-10
transmitter 12-12 , 12-20
Transmitter Buffer 12-28
Transmitter Clear-to-Send 12-20
Transmitter Clock Select 12-24
Transmitter Disable 12-26
Transmitter Empty 12-23
Transmitter Enable 12-26
transmitter mode 13-14
Transmitter Ready 12-23
Transmitter Ready-to-Send 12-19
transmitter serial data output 12-3
TRAP 1-6
TRAP instruction 3-10
Trigger Definition Register (TDR) 15-33
Trigger Response Control 15-33
TRST 16-3 , 16-8
Two masters 6-54
two-wire mode 6-54
U
UART 2-14 , 12-3 , 12-5
bus operation 12-16
interrupt acknowledge cycles 12-16
interrupts 8-5
programming model 12-16
signals 2-14
UART Clock-Select Register (UCSR) 12-24
UART Command Register (UCR) 12-24
UART command register (UCR) 12-6 , 12-9
UART Input Port Change Register (UIPCR) 12-28
UART Input Port Register (UIP) 12-32
UART Interrupt Mask Register (UIMR) 12-30
UART Interrupt Status Register (UISR) 12-29
UART Interrupt Vector Register (UIVR) 12-31
UART Mode Register 1 (UMR1) 12-17
UART Mode Register 2 (UMR2) 12-19
UART module
I/O driver routines 12-33
initialization routines 12-33
timer upper preload registers 12-31
timer/counter 12-3
valid start bit 12-9
UART Module Initialization 12-33 , 12-34
UART Output Port Data Register (UOP0-1) 12-32
UART Receive Buffer (URB) 12-28
UART Status Register (USR) 12-21
UART Transmitter Buffer (UTB) 12-28
UBG1, 2 12-31
Unassigned Opcodes 15-25
user mode 1-6 , 3-2
User Programming Model 1-8, 3-2
USR 12-11
V
Vector Base Register (VBR) 3-5
version number 16-4
W
WDEBUG 15-30
WDMREG 15-30
WRITE 15-19
Write A/D Register (WAREG/WDREG) 15-12
Write Control Register (WCREG) 15-23
write cycle 6-2
Write Debug Register (WDREG) 15-24
write enables 2-5 , 8-16 , 9-1
encoding 9-2
Write Memory Location (WRITE) 15-15
Write Transfer 6-14 , 6-15
Z
zero wait state 9-11
zero wait-state operation 6-30, 6-47
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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