Datasheet

Introduction
1-16 MCF5206e USER’S MANUAL MOTOROLA
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1.3.6 DRAM Controller
The MCF5206e DRAM controller provides a glueless interface for as many as two banks of
DRAM, each of which can be from 128 Kbytes to 256 Mbytes in size. The controller supports
an 8 bit, 16 bit, or 32 bit data bus. A unique addressing scheme allows for increases in
system memory size without rerouting address lines and rewiring boards. The controller
operates in fast page mode, burst-page mode, or in normal mode, and supports EDO
DRAMs.
DRAM operations are available to other external bus masters. The DRAM controller can
generate CAS and RAS for an external master and can continue to manage refresh
requests.
1.3.7 Direct Memory Access (DMA)
The MCF5206e provides 2 fully programmable DMA channels for quick data transfer.
Single- and dual-address mode is provided with the ability to program bursting and cycle
steal. Data transfers are 32 bits in length with packing and unpacking supported, along with
an auto-alignment option for efficient block transfers. DMA transfers can be initiated via
three mechanisms: S/W initiated; external requests; or from a UART interrupt.
1.3.8 UART modules
Two full duplex UART modules contain independent receivers and transmitters that can be
clocked by the UART internal timer. This timer is clocked by the system clock or an external
clock supplied by aTIN pin. Data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity,
and as many as 2 stop bits in 1/16 increments. Four-byte receive buffers and two-byte
transmit buffers minimize CPU service calls. The UART modules also provides several
error-detection and maskable-interrupt capabilities. Modem support includes request-to-
send (RTS) and clear-to-send (CTS) lines.
The system clock provides the clocking function via a programmable prescaler. You can
select full duplex, autoecho loopback, local loopback, and remote loopback modes. The
programmable UARTs can interrupt the CPU on various normal or error-condition events.
1.3.9 Timer Module
The timer module includes two general-purpose timers, each of which contains a free-
running 16-bit timer for use in any of three modes. One mode captures the timer value with
an external event. Another mode triggers an external signal or interrupts the CPU when the
timer reaches a set value, while a third mode counts external events. The timer unit has an
8-bit prescaler that allows for programming the clock input frequency, which is derived from
the system clock. The programmable timer-output pin generates either an active-low pulse
or toggles the output.
1.3.10 Motorola Bus (M-Bus) Module
The M-Bus interface is a two-wire, bidirectional serial bus that exchanges data between
devices and is compatible with the I
2
C Bus standard. The M-Bus minimizes the
interconnection between devices in the end system and is best suited for applications that
Fr
eescale S
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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