Datasheet

Introduction

MOTOROLA MCF5206e USER’S MANUAL 1-17

need occasional bursts of rapid communication over short distances among several

devices. Bus capacitance and the number of unique addresses limit the maximum

communication length and the number of devices that can be connected.

1.3.11 System Interface

The MCF5206e processor provides a glueless interface to 8-, 16-, and 32-bit SRAM, ROM,

and peripheral devices with independent programmable control of the assertion and

negation of chip selects and write enables. Programmable address and data-hold times can

be extended for a compatible interface to external devices and memory. The MCF5206e

also supports bursting ROMs.

1.3.11.1 EXTERNAL BUS INTERFACE. The bus interface controller transfers information

between the ColdFire core and memory, peripherals, or other masters on the external bus.

The external bus interface provides as many as 28 bits of address bus space, a 32-bit data

bus, and all associated control signals. This interface implements an extended synchronous

protocol that supports bursting operations. For nonsynchronous external memory and

peripherals, the MCF5206e processor provides an alternate asynchronous bus transfer

acknowledgment signal.

Simple two-wire request/acknowledge bus arbitration between the MCF5206e processor

and another bus master, such as a DMA device, is glueless with arbitration handled internal

to the MCF5206e processor. Alternately, an external bus arbiter can control more complex

three-wire (request, grant, busy) multiple-master bus arbitration, allowing overlapped bus

arbitration with one clock-bus handovers.

1.3.11.2 CHIP SELECTS . Eight programmable chip select outputs provide signals that

enable external memory and peripheral circuits for automatic wait-state insertion. These

signals also interface to 8 bit, 16 bit, or 32 bit ports. In addition, other external bus masters

can access chip selects. The upper four chip selects are multiplexed with A[27:24] of the

address bus and the four write enables. The base address, access permissions, and timing

waveforms are all programmable with configuration registers.

1.3.12 8-Bit Parallel Port (General-Purpose I/O)

An 8-bit general-purpose programmable parallel port serves as either an input or an output

on a bit-by-bit basis. The parallel port is multiplexed with PST[3:0] and DDATA[3:0] debug

signals.

1.3.13 Interrupt Controller

The interrupt controller provides user-programmable control of three or seven external

interrupt and five internal peripheral interrupts. You can program each internal interrupt to

any one of seven interrupt levels and four priority levels within each of these levels. You can

configure the three external interrupt signals as either fixed interrupt levels 1, 4, and 7, or as

a seven-level encoded interrupt. You can program the external interrupts to any one of the

four priority levels within the respective interrupt levels.

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