Datasheet

Introduction
1-18 MCF5206e USER’S MANUAL MOTOROLA
2
3
4
6
7
8
9
1
11
12
13
14
15
16
1.3.14 System Protection
The MCF5206e processor contains a 16-bit software watchdog timer with an 8-bit prescaler.
The programmable software watchdog timer provides either a level 7 interrupt or a hardware
reset on timeout. The MCF5206e processor also contains a reset status register that
indicates the cause of the last reset.
1.3.15 JTAG
To help with system diagnostics and manufacturing testing, the MCF5206e processor
includes dedicated user-accessible test logic that complies with the IEEE 1149.1 standard
for boundary scan testability, often referred to as Joint Test Action Group, or JTAG. For
more information, refer to the IEEE 1149.1 standard.
1.3.16 System Debug Interface
The ColdFire processor core debug interface supports real-time trace and background
debug mode. A four-pin Background Debug Mode (BDM) interface provides system debug.
The BDM is a proper subset of the BDM interface provided on Motorola’s 683XX Family of
parts.
In real-time trace, four status lines provide information on processor activity in real time (PST
pins). A 4-bit wide debug data bus (DDATA) displays operand data, which helps track the
machine’s dynamic execution path as the change-of-flow instructions execute. These
signals are multiplexed with an 8-bit parallel port for application development, which does
not use real-time trace.
1.3.17 Pinout and Package
The MCF5206e device is supplied in a 160-pin plastic quad flat pack package, at speeds of
45 MHz and 54 MHz, and is pin-compatible with the MCF5206 (DMA is muxed with timer).
It is available in 3.3V, with 5V-tolerant I/O.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...