Datasheet

Signal Description
2-2 MCF5206e USER’S MANUAL MOTOROLA
NOTE
The terms assert and negate are used throughout this section
to avoid confusion when dealing with a mixture of active-low
and active-high signals. The term assert or assertion indicates
that a signal is active or true, independent of the level
represented by a high or low voltage. The term negate or
negation indicates that a signal is inactive or false.
Table 2-1. MCF5206e Signal Index
SIGNAL NAME MNEMONIC FUNCTION
INPUT/
OUTPUT
Address[27:24]/
Chip Select[7:4]/
Write Enable[3:0]
A[27:24]/
CS
[7:4]/
WE
[3:0]
Upper four bits of the address bus/
Upper four chip selects enable peripherals at programmed addresses/
Write enables select individual bytes in memory
In,Out/
Out/
Out
Address A[23:0] Lower 24 bits of the address bus. A[4:2] indicate the interrupt level
during an IACK cycle
In,Out
Data D[31:0] Data bus used to transfer byte, word, or longword data In,Out
Chip Select[3:0] CS
[3:0] Enables peripherals at programmed addresses. CS[1] can indicate
IACK during an interrupt acknowledge cycle. CS[0]
provides relocatable
boot ROM capability
Out
Interrupt Priority Level/
Interrupt Request
IPL
[2]/IRQ[7]
IPL
[1]/IRQ[4]
IPL
[0]/IRQ[1]
Provides encoded interrupt priority level to processor/
Three individual external interrupts set to levels 7, 4, 1
In/
In
Read/Write R/W
Identifies read and write data transfers In,Out
Size SIZ[1:0] Indicates the data transfer size In,Out
Transfer Type TT[1:0] Indicates the transfer type: normal, CPU space/Interrupt acknowledge or
emulator mode
Out
Access Type & Mode ATM Time-multiplexed output signal indicating access type (instruction or
data) and access mode (supervisor or user)
Out
Transfer Start TS
Indicates the beginning of a bus cycle In,Out
Transfer Acknowledge TA
Synchronous transfer acknowledge. Asserted to indicate the successful
completion of a bus transfer.
In,Out
Asynchronous Transfer
Acknowledge
ATA
Asynchronous transfer acknowledge. Asserted to indicate the
successful completion of a bus transfer
In
Transfer Error Acknowledge TEA
Asserted to indicate an error condition exists for a bus transfer In
Bus Request BR Asserted by the MCF5206e to request bus mastership Out
Bus Grant BG
Asserted by bus arbiter to grant bus mastership privileges to the
MCF5206e
In
Bus Driven BD
Indicates the MCF5206e has assumed explicit bus mastership of the
external bus
Out
Clock Input CLK Input used to clock internal logic In
Reset RSTI
Processor reset In
Row Address Strobe RAS[1:0] Row address strobe for external DRAM Out
Column Address Strobe CAS[3:0] Column address strobe for external DRAM Out
DRAM Write DRAMW
Asserted on DRAM write cycles and negated on DRAM read cycles Out
Receive Data RxD[1], RxD[2] Receive serial data input for UART 1 and UART 2 In
Transmit Data TxD[1],TxD[2] Transmit serial data output for UART 1 and UART 2 Out
Request-To-Send RTS
[1] Indicates UART 1 is ready to receive data Out
Request-To-Send/
Reset Out
RTS[2]/RSTO RTSindicates UART 2 is ready to receive data/
RSTO
is the reset out signal
Out/
Out
Clear-To-Send CTS
[1], CTS[2] Indicates can transmit serial data for UART 1 and UART 2 In
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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