Datasheet

Signal Description
MOTOROLA MCF5206e USER’S MANUAL 2-3
2.2 ADDRESS BUS
These three-state bidirectional address signals indicate the following:
The address bus includes 24 dedicated address signals, A[23:0], and supports as many
as four additional configurable address signals, A[27: 24] (refer to Section 7.3.2.10 Pin
Assignment Register (PAR)). The address will appear only on the pins configured to be
address signals.
When an external master is using the MCF5206e as a slave DRAM controller, the external
master asserts TS
and places the transfer address on the address pins. The external
master then three-states the address signals and the MCF5206e drives the row address
and the column address on the address bus at the appropriate times.
DMA Request Input DREQ[0], DREQ[1] External DMA request inputs for channels 0 & 1 In
Timer Input/TIN[1] or DREQ[0] TIN[1], TIN[2] Clock input to timer or trigger input for timer value capture logic In
Timer Output/TOUT[1] or DREQ[1] TOUT[1], TOUT[2] Timer output waveform or pulse generation In,Out
Serial Clock Line SCL Clock signal for M-Bus module operation In,Out
Serial Data Line SDA Serial data port for M-Bus module operation In,Out
General Purpose I/O/
Processor Status
PP[7:4]/PST[3:0] Upper 4 bits of general purpose I/O port /
Internal processor status.
In,Out/
Out
General Purpose I/O/
Debug Data
PP[3:0]/DDATA[3:0]Lower 4 bits of general purpose I/O port /
Captured processor data and break-point status debug data
In,Out/
Out
Test Clock TCK JTAG clock signal In
Test Data Output/
Development Serial Output
TDO/DSO JTAG serial data out/
Debug serial out
Out/
Out
Test Mode Select/
Break Point
TMS/BKPT
JTAG mode select/
Debug mode breakpoint
In/
In
Test Data Input /
Development Serial Input
TDI/DSI JTAG serial data input/
Debug serial input
In/
In
Test Reset/
Development Serial Clock
TRST
/DSCLK Asynchronous JTAG reset input/
Debug serial clock input
In/
In
Motorola Test Mode MTMOD Selects JTAG or Debug signals In
High Impedance HIZ Output buffer three-state and master reset control In
Table 2-2. Address Bus
TYPE OF BUS TRANSFER/MEMORY SPACE ACCESSED ADDRESS BUS
Interrupt Acknowledge Transfer A[27:5] = $7FFFF, A[1:0]=$0, A[4:2] Interrupt Level being serviced
Chip Select Transfer Address of byte or most significant byte of word or longword being accessed
DRAM Transfer Row Address and Column Address indicating byte or most significant byte of
word or longword being accessed
Default Memory Address of byte or most significant byte of word or longword being accessed
Table 2-1. MCF5206e Signal Index (Continued)
SIGNAL NAME MNEMONIC FUNCTION
INPUT/
OUTPUT
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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