Datasheet

Signal Description
2-4 MCF5206e USER’S MANUAL MOTOROLA
2.2.1 Address Bus (A[27:24]/ CS[7:4]/ WE[0:3])
These multiplexed pins can serve as the most significant nibble of the address pins, chip-
selects, or as write enables. Programming the Pin Assignment Register (PAR) in the SIM
determines the function of each of these four multiplexed pins. During reset, these pins
are configured to be write enables.
When any of these pins are enabled as address lines in the PAR, they represent the most
significant bits of the address bus. A maximum of 256 Mbytes of memory is addressable
when all of these pins are programmed as address signals. Any of these pins that are
programmed as address lines have the same timing as the lower address lines A[23:0].
All address lines become valid during the same clock phase TS is asserted.
2.2.2 Address Bus (A[23:0])
The three-state bidirectional signals are the 24 least significant bits of the address bus.
For chip select and default memory transfers initiated by the ColdFire
®
core, the
MCF5206e outputs the address and increments the lower bits during burst transfers,
allowing the address bus to be directly connected to external memory. For DRAM
transfers initiated by the ColdFire core, the MCF5206e outputs the row address and
column address as specified by the DRAM control registers.
The MCF5206e does not output the address during alternate or external master initiated
chip select and default memory transfers. When an external master is using the
MCF5206e as a slave DRAM controller, the external master asserts TS and places the
row and column address on the address pins. The external master drives the address
signals to a high-impedence state and the MCF5206e then drives the row address and
the column address on the address bus at the appropriate times.
2.2.3 Data Bus (D[31:0])
The three-state bidirectional signals provide a nonmultiplexed general purpose data path
between the MCF5206e and all other devices in the system. During a read bus transfer,
data is registered from the bus on the rising clock edge during which TA is asserted, or
during the rising clock in which internal asynchronous transfer acknowledge is asserted
or internal transfer acknowledge is asserted.
The data bus port width is initially configured by the values on IPL[1]/IRQ[4] and IPL[0]/
IRQ[1] during reset. Port width is individually programmed for each chip select region and
DRAM bank, and is globally configured for a memory region not matching chip select
settings or DRAM memory, referred to as default memory. The data bus transfers byte,
word, or longword sized data. All 32 bits of the data bus are driven during writes,
regardless of port width or operand size.
2.3 CHIP SELECTS
The MCF5206e provides as many eight programmable chip selects that can directly
interface with SRAM, EPROM, EEPROM, and peripherals.
Fr
eescale S
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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