Datasheet

Signal Description
2-8 MCF5206e USER’S MANUAL MOTOROLA
Table 2-4. Interrupt Levels for Encoded External Interrupts
During reset, the interrupt-priority level/interrupt request pins are sampled to define port
size and wait-state generation for CS Tables 2-5 and 2-6 show the reset values for wait
states and port size for CS[0] based on the these pins.
2.5 BUS CONTROL SIGNALS
2.5.1 Read/Write (R/W
) Signal
This three-state bidirectional signal defines the data transfer direction for the current bus
cycle. A high (logic one) level indicates a read cycle while a low (logic zero) level indicates
a write cycle. When an alternate bus master is controlling the bus, the MCF5206e
monitors this signal to determine if chip select or DRAM control signals need to be
asserted.
IPL[2]/IRQ[7] IPL[1]/IRQ[4] IPL[0]/IRQ[1]
INTERRUPT LEVEL
INDICATED
000 7
001 6
010 5
011 4
100 3
101 2
110 1
1 1 1 No Interrupt
Table 2-5. Boot CS[0] Automatic Acknowledge (AA) Enable
IPL[2]/
IRQ
[7]
INITIAL CS
[0] AA
0 Disabled
1 Enabled with 15 wait states
Table 2-6. Interrupt Request Encodings for CS[0]
IPL[1]/
IRQ
[4]
IPL
[0]/
IRQ
[1]
INITIAL CS[0] PORT SIZE
0 0 32 bit port
0 1 8 bit port
1 0 16 bit port
1 1 16 bit port
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...