Datasheet

Signal Description
2-10 MCF5206e USER’S MANUAL MOTOROLA
2.5.5 Transfer Start (TS)
The MCF5206e asserts this three-state bidirectional active-low signal for one clock period
to indicate the start of each bus cycle. During alternate master accesses, the MCF5206e
monitors transfer start (TS) to detect the start of each alternate master bus cycle to
determine if chip select or DRAM control signals need to be asserted.
2.5.6 Transfer Acknowledge (TA)
This three-state bidirectional active-low synchronous signal indicates the completion of a
requested data transfer operation. During transfers initiated by the MCF5206e, transfer
acknowledge (TA) is an input signal from the referenced slave device indicating
completion of the transfer.
TA is not used for termination during DRAM accesses initiated by the MCF5206e.
When an external master is controlling the bus, TA may be driven as an output by the
MCF5206e or may be driven by the referenced slave device to indicate the completion of
the requested data transfer. If the alternate master requested transfer is to a chip select
or default memory, the assertion of TA is controlled by the number of wait states and the
setting of the Elternate Master Automatic Acknowledge (EMAA) bit in the Chip Select
Control Registers (CSCRs) or the Default Memory Control Register (DMCR). If the
alternate master requested transfer is a DRAM access, TA is driven by the MCF5206e as
an output and asserted at the completion of the transfer.
2.5.7 Asynchronous Transfer Acknowledge (ATA)
This active-low asynchronous input signal indicates the completion of a requested data
transfer operation. Asynchronous transfer acknowledge (ATA
) is an input signal from the
referenced slave device indicating completion of the transfer. ATA is synchronized
internal to the MCF5206e.
01
(DMA Access) DMA Data 1 0
10
(Debug Access)
Supervisor Code 1 1
Supervisor Data 0 1
11
(CPU Space/
Acknowledge Access)
CPU Space - MOVEC Instruction 0 0
Interrupt Acknowledge - level 7 1 0
Interrupt Acknowledge - level 6 1 0
Interrupt Acknowledge - level 5 1 0
Interrupt Acknowledge - level 4 1 0
Interrupt Acknowledge - level 3 1 0
Interrupt Acknowledge - level 2 1 0
Interrupt Acknowledge - level 1 1 0
Table 2-9. ATM Encoding (Continued)
TRANSFER TYPE INTERNAL TRANSFER MODIFIER ATM (TS=0) ATM (TS=1)
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