Datasheet

Signal Description

MOTOROLA MCF5206e USER’S MANUAL 2-11

NOTE

The internal synchronized version of asynchronous transfer

acknowledge (ATA) will be referred to as “internal

asynchronous transfer acknowledge (ATA).” Because of the

time required to internally synchronize ATA

during a read

cycle, data is latched on the falling edge of CLK when the

internal ATA

is asserted. Consequently, data must remain

valid for at least one and a half clock cycles after the assertion

of ATA. Similarly, during a write cycle, data is driven until the

falling edge of CLK when the internal ATA is asserted.

ATA must be driven for one full clockto ensure that the MCF5206e properly synchronizes

the signal. ATA is not used for termination during DRAM accesses.

2.5.8 Transfer Error Acknowledge (TEA)

This active-low input signal is asserted by the external slave to indicate an error condition

for the current transfer. The assertion of transfer error acknowledge (TEA) causes the

MCF5206e to immediately abort the bus cycle. The assertion of TEA has precedence over

the assertion of ATA and TA.

NOTE

TEA can be asserted to a maximum of one clock after the

assertion of ATA and still be recognized.

TEA has no affect during DRAM accesses.

2.6 BUS ARBITRATION SIGNALS

2.6.1 Bus Request (BR

)

This active-low output signal indicates to an external arbiter that the MCF5206e needs

use of the bus for one or more bus cycles. BR is negated when the MCF5206e begins an

access to the external bus, and remains negated until another internal request occurs with

BG negated.

2.6.2 Bus Grant (BG)

An external arbiter asserts this active-low input signal to indicate that the MCF5206e can

become master of the external bus at the next rising edge of CLK. When the arbiter

negates BG, the MCF5206e relinquishes the bus as soon as the current transfer is

complete, provided the bus lock bit in the SIMR is not set. If the bus lock bit is set, the

MCF5206e will retain bus mastership until the bus lock bit is cleared. The external arbiter

must not grant the bus to any other master until the MCF5206e negates BD

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