Datasheet

Signal Description

2-12 MCF5206e USER’S MANUAL MOTOROLA

2.6.3 Bus Driven (BD)

The MCF5206e asserts this active-low output signal to indicate it has assumed explicit

mastership of the external bus. The MCF5206e will assert BD if BG is asserted and either

the MCF5206e has a pending bus transfer or the bus lock bit in the SIMR is set to 1. If the

MCF5206e is granted mastership of the external bus, but does not have a pending bus

transfer and the bus lock bit in the SIMR is cleared, the BD signal is not asserted (implicit

mastership of the bus is assumed).

If BG is negated to the MCF5206e during a bus transfer and the bus lock bit in the SIMR

is cleared, the MCF5206e completes the last transfer of the current access, negate BD,

and three-states all bus signals on the rising edge of CLK. If the MCF5206e loses bus

ownership during an idle bus period with BD asserted and the bus lock bit in the SIMR

cleared, the MCF5206e negates BD and three-states all bus signals on the next rising

edge of CLK. If the MCF5206e loses bus ownership during an idle bus period with BD

asserted and the bus lock bit in the SIMR set to 1, the MCF5206e continues to assert BD

and maintains explicit ownership of the external bus until the bus lock bit in the SIMR is

cleared.

2.7 CLOCK AND RESET SIGNALS

2.7.1 Clock Input (CLK)

CLK is the MCF5206e synchronous clock. CLK clocks or sequences the MCF5206e

internal logic and external signals.

2.7.2 Reset (RSTI)

Asserting the active-low RSTI input causes the MCF5206e processor to enter reset

exception processing. When RSTI is recognized, the address bus, data bus, TT, SIZ,

R/W, ATM and TS are three-stated; BR and BD are negated.

If RSTI

is asserted with HIZ asserted, the MCF5206e enters master reset mode. In this

reset mode, the entire MCF5206e (including the DRAM controller refresh circuitry) is

reset. You must use master reset for all power-on resets.

If RSTI is asserted with HIZ negated, the MCF5206e enters normal reset mode. In this

reset mode, the DRAM controller refresh circuitry is not reset and continues to generate

refresh cycles at the programmed rate and with the programmed waveform timing.

2.7.3 Reset Out (RTS[2]/RSTO)

RTS[2] is multiplexed with the RSTO signal. Programming the Pin Assignment Register

(PAR) in the SIM determines the function of this pin. During reset, this pin is configured to

be RSTO.

RSTO is an output that drives peripherals to reset. RSTO is asserted no more than two

clocks after the assertion of RSTI

, and RSTO remains asserted for at least 31 clocks after

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