Datasheet

Signal Description
MOTOROLA MCF5206e USER’S MANUAL 2-13
the negation of RSTI. RSTO is also asserted for at least 31 clocks on a software watchdog
timeout that is programmed to generate a reset.
2.8 DRAM CONTROLLER SIGNALS
The following DRAM signals provide a glueless interface to external DRAM.
2.8.1 Row Address Strobes (RAS[1:0])
These active-low output signals provide control for the row address strobe (RAS) input
pins on industry-standard DRAMs. There is one RAS output for each DRAM bank: RAS[0]
controls DRAM bank 0 and RAS[1] controls DRAM bank 1. You can customize RAS timing
to match the specifications of the DRAM being used by programming the DRAMC Timing
Register (see Section 7.3.2.10 Pin Assignment Register (PAR)).
2.8.2 Column Address Strobes (CAS[3:0])
These active-low output signals provide control for the column address strobe (CAS) input
pins on industry-standard DRAMs. The CAS signals enable data byte lanes: CAS[0]
controls access to D[31:24], CAS[1] to D[23:16], CAS[2] to D[15:8], and CAS[3] to D[7:0].
You should use CAS[3:0] for a 32 bit wide DRAM bank, CAS[1:0] for a 16 bit wide DRAM
bank, and CAS[0] for an 8 bit wide DRAM bank. Table 2-10 shows which CAS signals are
asserted based on the operand size, the DRAM port size, and the address bits A[1:0]. You
can customize CAS timing to match the specifications of the DRAM by programming the
DRAM Controller Timing Register (see Section 10.4.2.2 DRAM Controller Timing
Register (DCTR)).
.
Table 2-10. CAS Assertion
OPERAND SIZE PORT SIZE SIZ[1] SIZ[0] A[1] A[0]
CAS
[0] CAS[1] CAS[2] CAS[3]
D[31:24] D[23:16] D[15:8] D[7:0]
BYTE
8 bit 0 1
000111
010111
100111
110111
16 bit 0 1
000111
011011
100111
111011
32 bit 0 1
000111
011011
101101
111110
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