Datasheet

Signal Description
2-14 MCF5206e USER’S MANUAL MOTOROLA
2.8.3 DRAM Write (DRAMW)
This active-low output signal is asserted during DRAM write cycles and negated during
DRAM read cycles. The DRAMW signal is negated during refresh cycles and is provided
(in addition to the R/W signal) to allow refreshes to occur during non-DRAM cycles
(regardless of the state of the R/W signal). The R/W signal indicates the direction of all
bus transfers, while DRAMW is valid only during DRAM transfers.
2.9 UART MODULE SIGNALS
The signals listed below transfer serial data between the two UART modules (UART 1 and
UART 2) and external peripherals.
2.9.1 Receive Data (RxD[1], RxD[2])
These are the inputs on which serial data is received by the UART modules. RxD[1]
corresponds to UART 1 and RxD[2] corresponds to UART 2. Data is sampled on RxD[1]
and RxD[2] on the rising edge of the serial clock source, with the least significant bit
received first.
WORD
8 bit 1 0
000111
010111
100111
110111
16 bit 1 0
000011
100011
32 bit 1 0
000011
101100
LONG WORD
8 bit 0 0
000111
010111
100111
110111
16 bit 0 0
000011
100011
32 bit 00000000
LINE
8 bit 1 1
000111
010111
100111
110111
16 bit 1 1
000011
100011
32 bit 11000000
Table 2-10. CAS Assertion (Continued)
OPERAND SIZE PORT SIZE SIZ[1] SIZ[0] A[1] A[0]
CAS
[0] CAS[1] CAS[2] CAS[3]
D[31:24] D[23:16] D[15:8] D[7:0]
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eescale S
emiconduct
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