Datasheet

Signal Description

MOTOROLA MCF5206e USER’S MANUAL 2-15

2.9.2 Transmit Data (TxD[1], TxD[2])

The UART modules transmit serial data on these outputs. TxD[1] corresponds to UART 1

and TxD[2] corresponds to UART 2. Data is transmitted on the falling edge of the serial

clock source, with the least significant bit transmitted (LSB) first. When no data is being

transmitted or the transmitter is disabled, these two signals are held high. TxD[1] and

TxD[2] are also held high in local loopback mode.

2.9.3 Request To Send (RTS[1], RTS[2]/RSTO)

RTS[2] is multiplexed with the RSTO signal. Programming the Pin Assignment Register

(PAR) in the SIM determines the function of this pin. During reset, this pin is configured to

be RSTO.

The request-to-send output indicates to the peripheral device that the UART module is

ready to receive data. RTS

[1] corresponds to UART 1 and RTS[2] corresponds to UART

2.9.4 Clear To Send (CTS[1], CTS[2])

Peripherals drive these inputs to indicate to the UART module that it can begin data

transmission. CTS[1] corresponds to UART 1 and CTS[2] corresponds to UART 2.

2.10 TIMER MODULE SIGNALS

The signal descriptions that follow are the external interface to the two general purpose

timer modules (Timer 1 and Timer 2).

2.10.1 Timer Input (TIN[2], TIN[1])

You can program the timer input to be the clock for the timer module. You can also

program the timer module to trigger a capture on the rising edge, falling edge, or both

edges of the timer input. TIN[1] corresponds to Timer 1 and TIN[2] corresponds to Timer

2. TIN[1] is muxed with DREQ[0]. The reset state of the dual function TIN[1] pin is for timer

operation.

2.10.2 Timer Output (TOUT[2], TOUT[1])

The programmable timer output pulses or toggles when the timer reaches the

programmed count value. TOUT[1] corresponds to Timer 1 and TOUT[2] corresponds to

Timer 2. The reset state of the dual function TOUT[1] pin is for timer operation.

2.11 DMA MODULE SIGNALS

The signal descriptions that follow are the external interface to the two DMA channels

(DREQ[0] and DREQ[1]).

2.11.1 DMA Request (DREQ[0], DREQ[1])

DREQ[0] is multiplexed with the TIN[1] pin and DREQ[1] is multiplexed with the TOUT[1]

pin. Refer to Figure 2.1. The reset state of the timer/DMA dual function pins is for the timer

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