Datasheet

Signal Description

MOTOROLA MCF5206e USER’S MANUAL 2-17

These outputs indicate the MCF5206e processor status. During debug mode, the timing

is synchronous with the processor clock (CLK) and the status is not related to the current

bus transfer. Table 2-11 shows the encodings of PST[3:0].

2.14.2 Debug Data (PP[3:0]/DDATA[3:0])

The debug data signals are multiplexed with general purpose I/O signals. Programming

the Pin Assignment Register (PAR) in the SIM determines the function of these pins.

During reset, these pins are configured as general purpose inputs.

The DDATA[3:0] outputs display captured processor data and breakpoint status. See

Section 15: Debug Support section for additional information on this bus.

2.14.3 Development Serial Clock (TRST/DSCLK)

The MTMOD signal determines the function of this dual-purpose pin. If MTMOD= 0, the

TRST

function is selected. If MTMOD=1, the DSCLK function is selected. MTMOD should

not be changed while RSTI = 1.

The DSCLK input signal is used as the development serial clock for the serial interface to

the debug module.The maximum frequency for the DSCLK signal is 1/2 the CLK

frequency. See Section 15: Debug Support section for additional information on this

signal.

Table 2-11. Processor Status Encodings

PST[3:0] DEFINITION

0000 Continue execution

0001 Begin execution of an instruction

0010 Reserved

0011 Entry into user mode

0100 Begin execution of PULSE instruction

0101 Begin execution of taken branch

0110 Reserved

0111 Begin execution of RTE instruction

1000 Reserved

1001 Reserved

1010 Reserved

1011 Reserved

1100 † Exception processing

1101 † Emulator mode entry exception processing

1110 † Processor is stopped, waiting for interrupt

1111 † Processor is halted

† These encodings are asserted for multiple cycles.

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