Datasheet

ColdFire Core
3-2 MCF5206e USER’S MANUAL MOTOROLA
2
3
4
5
6
7
8
9
10
12
13
14
15
16
1
The processor core is comprised of two separate pipelines that are decoupled by an
instruction buffer. The Instruction Fetch Pipeline (IFP) is responsible for instruction address
generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that
holds prefetched instructions awaiting execution in the Operand Execution Pipeline (OEP).
The OEP includes two pipeline stages. The first stage decodes instructions and selects
operands (DSOC); the second stage (AGEX) performs instruction execution and calculates
operand effective addresses, if needed.
3.2 PROCESSOR REGISTER DESCRIPTION
The following paragraphs describe the processor registers in the user and supervisor
programming models. The appropriate programming model is selected based on the
privilege level (user mode or supervisor mode) of the processor as defined by the S bit of
the status register.
3.2.1 User Programming Model
Figure 3-2 illustrates the user programming model. The model is the same as for M68000
Family microprocessors, consisting of the following registers:
• 16 general-purpose 32-bit registers (D0–D7, A0–A7)
• 32-bit program counter (PC)
• 8-bit condition code register (CCR)
3.2.1.1 DATA REGISTERS (D0–D7). Registers D0–D7 are used as data registers for bit (1
bit), byte (8 bit), word (16 bit) and longword (32 bit) operations and can also be used as index
registers.
3.2.1.2 ADDRESS REGISTERS (A0–A6). These registers can be used as software stack
pointers, index registers, or base address registers as well as for word and longword
operations.
3.2.1.3 STACK POINTER (A7). The ColdFire architecture supports a single hardware
stack pointer (A7) for explicit references as well as for implicit ones during stacking for
subroutine calls and returns and exception handling. The initial value of A7 is loaded from
the reset exception vector, address $0. The same register is used for both user and
supervisor mode as well as word and longword operations.
A subroutine call saves the PC on the stack and the return restores it from the stack. Both
the PC and the SR are saved on the stack during the processing of exceptions and
interrupts. The return from exception instruction restores the SR and PC values from the
stack.
3.2.1.4 PROGRAM COUNTER. The PC contains the address of the currently executing
instruction. During instruction execution and exception processing, the processor
automatically increments the contents of the PC or places a new value in the PC, as
appropriate. For some addressing modes, the PC can be used as a pointer for PC-relative
operand addressing.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...