Datasheet

ColdFire Core
MOTOROLA MCF5206e USER’S MANUAL 3-5
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bits indicate the following states for the processor: trace mode (T-bit), supervisor or user
mode (S bit), and master or interrupt state (M).
T– trace enable
When set, the processor will perform a trace exception after every instruction.
S– supervisor / user state
Denotes whether the processor is in supervisor mode (S=1) or user mode (S=0).
M– master / interrupt state
This bit is cleared by an interrupt exception, and can be set by software during execution of
the RTE or move to SR instructions.
I[2:0]– interrupt priority mask
Defines the current interrupt priority. Interrupt requests are inhibited for all priority levels less
than or equal to the current priority, except the edge-sensitive level 7 request, which cannot
be masked.
3.2.4.2 VECTOR BASE REGISTER (VBR). The VBR contains the base address of the
exception vector table in memory. The displacement of an exception vector is added to the
value in this register to access the vector table. The lower 20 bits of the VBR are not
implemented by ColdFire processors; they are assumed to be zero, forcing the table to be
aligned on a 1 MByte boundary.
3.3 EXCEPTION PROCESSING OVERVIEW
Exception processing for ColdFire processors is streamlined for performance. The ColdFire
processors provide a simplified exception processing model. The next section details the
model.Differences from previous 68000 Family processors include:
• A simplified exception vector table
• Reduced relocation capabilities using the vector base register
• A single exception stack frame format
• Use of a single self-aligning system stack
ColdFire processors use an instruction restart exception model but do require more software
support to recover from certain access errors. See subsection 3.5.1 Access Error
Exception for details.
Exception processing is comprised of four major steps and can be defined as the time from
the detection of the fault condition until the fetch of the first handler instruction has been
initiated.
SYSTEM BYTE CONDITION CODE REGISTER (CCR)
1514131211109876543210
T 0 S M 0 I[2:0] 0 0 0 X N Z V C
Status Register
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