Datasheet

ColdFire Core
MOTOROLA MCF5206e USER’S MANUAL 3-7
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The V2 Core processors inhibit sampling for interrupts during the first instruction of all
exception handlers. This allows any handler to effectively disable interrupts, if necessary, by
raising the interrupt mask level contained in the status register.
3.4 EXCEPTION STACK FRAME DEFINITION
The exception stack frame is shown in Figure 3-5. The first longword of the exception stack
frame contains the 16-bit format/vector word (F/V) and the 16-bit status register, and the
second longword contains the 32-bit program counter address.
The 16-bit format/vector word contains 3 unique fields:
• A 4-bit format field at the top of the system stack is always written with a value of
{4,5,6,7} by the processor indicating a two-longword frame format. See Table 3-2.
Table 3-1. Exception Vector Assignments
VECTOR
NUMBER(S)
VECTOR
OFFSET (HEX)
STACKED
PROGRAM
COUNTER
ASSIGNMENT
0 $000 - Initial stack pointer
1 $004 - Initial program counter
2 $008 Fault Access error
3 $00C Fault Address error
4 $010 Fault Illegal instruction
5-7 $014-$01C - Reserved
8 $020 Fault Privilege violation
9 $024 Next Trace
10 $028 Fault Unimplemented line-a opcode
11 $02C Fault Unimplemented line-f opcode
12 $030 Next Debug interrupt
13 $034 - Reserved
14 $038 Fault Format error
15 $03C Next Uninitialized interrupt
16-23 $040-$05C - Reserved
24 $060 Next Spurious interrupt
25-31 $064-$07C Next Level 1-7 autovectored interrupts
32-47 $080-$0BC Next Trap # 0-15 instructions
48-63 $0C0-$0FC - Reserved
64-255 $100-$3FC Next User-defined interrupts
“Fault” refers to the PC of the instruction that caused the exception
“Next” refers to the PC of the next instruction that follows the instruction that caused the fault.
Figure 3-5. Exception Stack Frame Form
FORMAT FS[3:0] VECTOR[7:0] FS[1:0] STATUS REGISTER
PROGRAM COUNTER[31:0]
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