Datasheet

ColdFire Core
3-10 MCF5206e USER’S MANUAL MOTOROLA
2
3
4
5
6
7
8
9
10
12
13
14
15
16
1
Because ColdFire processors do not support any hardware stacking of multiple exceptions,
it is the responsibility of the operating system to check for trace mode after processing other
exception types. As an example, consider the execution of a TRAP instruction while in trace
mode. The processor will initiate the TRAP exception and then pass control to the
corresponding handler. If the system requires that a trace exception be processed, it is the
responsibility of the TRAP exception handler to check for this condition (SR[15] in the
exception stack frame asserted) and pass control to the trace handler before returning from
the original exception.
3.5.6 Debug Interrupt
This special type of program interrupt is discussed in detail in Section 15: Debug support.
This exception is generated in response to a hardware breakpoint register trigger. The
processor does not generate an IACK cycle but rather calculates the vector number
internally (vector number 12).
3.5.7 RTE and Format Error Exceptions
When an RTE instruction is executed, the processor first examines the 4-bit format field to
validate the frame type. For a ColdFire 5200 processor, any attempted execution of an RTE
where the format is not equal to {4,5,6,7} generates a format error. The exception stack
frame for the format error is created without disturbing the original RTE frame and the
stacked PC pointing to the RTE instruction.
The selection of the format value provides some limited debug support for porting code from
68000 applications. On 680x0 Family processors, the SR was located at the top of the stack.
On those processors, bit[30] of the longword addressed by the system stack pointer is
typically zero. Thus, if an RTE is attempted using this “old” format, it generates a format error
on a ColdFire 5200 processor.
If the format field defines a valid type, the processor: (1) reloads the SR operand, (2) fetches
the second longword operand, (3) adjusts the stack pointer by adding the format value to the
auto-incremented address after the fetch of the first longword, and then (4) transfers control
to the instruction address defined by the second longword operand within the stack frame.
3.5.8 TRAP Instruction Exceptions
The TRAP #n instruction always forces an exception as part of its execution and is useful
for implementing system calls.
3.5.9 Interrupt Exception
The interrupt exception processing, with interrupt recognition and vector fetching, includes
uninitialized and spurious interrupts as well as those where the requesting device supplies
the 8-bit interrupt vector. Autovectoring may optionally be supported through the System
Integration module (SIM). Refer to Section 8: System Integration Module to see if this is
supported on the MCF5206e.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...