Datasheet

ColdFire Core
3-12 MCF5206e USER’S MANUAL MOTOROLA
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1. The operand execution pipeline (OEP) is loaded with the opword and all required ex-
tension words at the beginning of each instruction execution. This implies that the OEP
does not wait for the instruction fetch pipeline (IFP) to supply opwords and/or exten-
sion words.
2. The OEP does not experience any sequence-related pipeline stalls. For ColdFire 5200
processors, the most common example of this type of stall involves consecutive store
operations, excluding the MOVEM instruction. For all STORE operations (except
MOVEM), certain hardware resources within the processor are marked as “busy” for
two clock cycles after the final DSOC cycle of the store instruction. If a subsequent
STORE instruction is encountered within this 2-cycle window, it will be stalled until the
resource again becomes available. Thus, the maximum pipeline stall involving con-
secutive STORE operations is 2 cycles. The MOVEM instruction uses a different set
of resources and this stall does not apply.
3. The OEP completes all memory accesses without any stall conditions caused by the
memory itself. Thus, the timing details provided in this section assume that an infinite
zero-wait state memory is attached to the processor core.
4. All operand data accesses are aligned on the same byte boundary as the operand
size, i.e., 16 bit operands aligned on 0-modulo-2 addresses, 32 bit operands aligned
on 0-modulo-4 addresses.
If the operand alignment fails these guidelines, it is misaligned. The processor core
decomposes the misaligned operand reference into a series of aligned accesses as shown
in Table 3-4.
3.6.2 MOVE Instruction Execution Times
The execution times for the MOVE.{B,W} instructions are shown in Table 3-5, while Table
3-6 provides the timing for MOVE.L.
For all tables in this section, the execution time of any instruction using the PC-relative
effective addressing modes is the same for the comparable An-relative mode.
The nomenclature “xxx.wl” refers to both forms of absolute addressing, xxx.w and xxx.l.
Table 3-4. Misaligned Operand References
ADDRESS[1:0] SIZE
KBUS
OPERATIONS
ADDITIONAL
C(R/W)
X1 Word Byte, Byte
2(1/0) if read
1(0/1) if write
X1 Long Byte, Word, Byte
3(2/0) if read
2(0/2) if write
10 Long Word, Word
2(1/0) if read
1(0/1) if write
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eescale S
emiconduct
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