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MOTOROLA

MCF5206e USER’S MANUAL vii

TABLE OF CONTENTS

Paragraph Page

Number Title Number

Section 1

Introduction

1.1 Background ..........................................................................................1-1

1.2 MCF5206e Features ............................................................................1-2

1.3 Functional Blocks .................................................................................1-4

1.3.1 ColdFire Processor Core ............................................................1-5

1.3.1.1 Processor States ............................................................1-6

1.3.1.2 Programming Model .......................................................1-6

1.3.1.3 MAC Registers Summary .............................................1-10

1.3.1.4 Addressing Capabilities Summary ................................1-10

1.3.1.5 Instruction Set Overview ...............................................1-10

1.3.2 MAC Module .............................................................................1-15

1.3.3 Hardware Divide Module ..........................................................1-15

1.3.4 Instruction Cache .....................................................................1-15

1.3.5 Internal SRAM ..........................................................................1-15

1.3.6 DRAM Controller ......................................................................1-16

1.3.7 Direct Memory Access (DMA) ..................................................1-16

1.3.8 UART Modules .........................................................................1-16

1.3.9 Timer Module ...........................................................................1-16

1.3.10 Motorola Bus (M-Bus) Module ..................................................1-16

1.3.11 System Interface ......................................................................1-17

1.3.11.1 External Bus Interface ..................................................1-17

1.3.11.2 Chip Selects ..................................................................1-17

1.3.12 8-Bit Parallel Port (General Purpose I/O) .................................1-17

1.3.13 Interrupt Controller ...................................................................1-17

1.3.14 System Protection ....................................................................1-18

1.3.15 JTAG ........................................................................................1-18

1.3.16 System Debug Interface ...........................................................1-18

1.3.17 Pinout and Package .................................................................1-18

Section 2

Signal Description

2.1 Introduction ...........................................................................................2-1

2.2 Address Bus .........................................................................................2-3

2.2.1 Address Bus (A[27:24]/ CS[7:4]/ WE[0:3]) .................................2-4

2.2.2 Address Bus (A[23:0]) ................................................................2-4

2.2.3 Data Bus (D[31:0]) ......................................................................2-4

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Freescale Semiconductor, Inc.

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Go to: www.freescale.com

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