Datasheet

MOTOROLA MCF5206e USER’S MANUAL 4-1

SECTION 4

INSTRUCTION CACHE

4.1 FEATURES OF INSTRUCTION CACHE

• 4 KByte Direct-Mapped Cache

• Single-Cycle Access on Cache Hits

• Physically Located on ColdFire

Core's High-Speed Local Bus

• Nonblocking Design to Maximize Performance

• 16 Byte Line-Fill Buffer

• Configurable Cache Miss-Fetch Algorithm

4.2 INSTRUCTION CACHE PHYSICAL ORGANIZATION

The instruction cache is a direct-mapped single-cycle memory, organized as 256 lines, each

containing 16 Bytes. The memory storage consists of a 256-entry tag array (containing

addresses and a valid bit), and the data array containing 4 KBytes of instruction data,

organized as 1024 x 32 bits.

The two memory arrays are accessed in parallel: bits [11:4] of the instruction fetch address

provide the index into the tag array, and bits [11:2] addressing the data array. The tag array

outputs the address mapped to the given cache location along with the valid bit for the line.

This address field is compared to bits [31:12] of the instruction fetch address from the local

bus to determine if a cache hit in the memory array has occurred. If the desired address is

mapped into the cache memory, the output of the data array is driven onto the ColdFire

core's local data bus completing the access in a single cycle.

The tag array maintains a single valid bit per line entry. Accordingly, only entire 16 Byte lines

are loaded into the instruction cache.

The instruction cache also contains a 16 Byte fill buffer that provides temporary storage for

the last line fetched in response to a cache miss. With each instruction fetch, the contents

of the line fill buffer are examined. Thus, each instruction fetch address examines both the

tag memory array and the line fill buffer to see if the desired address is mapped into either

hardware resource. A cache hit in either the memory array or the line-fill buffer is serviced

in a single cycle. Because the line fill buffer maintains valid bits on a longword basis, hits in

the buffer can be serviced immediately without waiting for the entire line to be fetched.

If the referenced address is not contained in the memory array or the line-fill buffer, the

instruction cache initiates the required external fetch operation. In most situations, this is a

16-byte line-sized burst reference.

eescale S

emiconduct

, I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

nc...