Datasheet

Instruction Cache
4-2 MCF5206e USER’S MANUAL MOTOROLA
The hardware implementation is a nonblocking design, meaning the ColdFire core's local
bus is released after the initial access of a miss. Thus, the cache or the SRAM module
can service subsequent requests while the remainder of the line is being fetched and
loaded into the fill buffer.
Figure 4-1. Instruction Cache Block Diagram
4.3 INSTRUCTION CACHE OPERATION
The instruction cache is physically connected to the ColdFire core's local bus, allowing it
to service all instruction fetches from the ColdFire core and certain memory fetches
initiated by the debug module. Typically, the debug module's memory references appear
as supervisor data accesses but the unit can be programmed to generate user-mode
accesses and/or instruction fetches. The instruction cache processes any instruction fetch
access in the normal manner.
31
11
4
3
0
1
2
31
4
=
=
31
9
31
0
‘127
31
0
0
LOCAL ADDRESS BUS
LINE
BUFFER
ADDRESS
EXTERNAL DATA[31:0]
LINE BUFFER DATA STORAGE
MUX
DATA
MUX
FILL HIT
TAG
VALID
LOCAL DATA BUS
TAG HIT
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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