Datasheet

Instruction Cache
MOTOROLA MCF5206e USER’S MANUAL 4-5
contents of the fill buffer versus its corresponding cache location. At the time of the miss,
the hardware indicator is set, marking the fill buffer as “most recently used.” If a
subsequent access occurs to the cache location defined by bits [8:4] of the fill buffer
address, the data in the cache memory array is now most recently used, so the hardware
indicator is cleared. In all cases, the indicator defines whether the contents of the line fill
buffer or the memory data array are most recently used. At the time of the next cache
miss, the contents of the line-fill buffer are written into the memory array if the entire line
is present, and the fill buffer data is still most recently used compared to the memory array.
The fill buffer can also be used as temporary storage for line-sized bursts of non-
cacheable references under control of CACR[10]. With this bit set, a noncacheable
instruction fetch is processed as defined by Table 4-2. For this condition, the fill buffer is
loaded and subsequent references can hit in the buffer, but the data is never loaded into
the memory array.
Table 4-2 shows the relationship between CACR bits 31 and 10 and the type of instruction
fetch.
4.4 INSTRUCTION CACHE PROGRAMMING MODEL
Three supervisor registers define the operation of the instruction cache and local bus
controller: the Cache Control Register (CACR) and two Access Control Registers (ACR0,
ACR1).
4.4.1 Instruction Cache Registers Memory Map
Table 4-3 below shows the memory map of the Instruction cache and access control
registers.
The following lists several keynotes regarding the programming model table:
• The Cache Control Register and Access Control Registers can only be accessed in
supervisor mode using the MOVEC instruction with an Rc value of $002, $004 and
$005, respectively.
Table 4-2. Instruction Cache Operation as Defined by CACR[31,10]
CACR[31] CACR[10] TYPE OF INSTR. FETCH DESCRIPTION
0 0 N/A Instruction cache is completely disabled; all fetches are word,
longword in size.
0 1 N/A All fetches are word, longword in size
1 X Cacheable Fetch size is defined by Table 4-1 and contents of the line-fill
buffer can be written into the memory array
1 0 Noncacheable All fetches are longword in size, and not loaded into the line-fill
buffer
1 1 Noncacheable Fetch size is defined by Table 4-1 and loaded into the line-fill
buffer, but are never written into the memory array.
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