Datasheet

Instruction Cache
4-6 MCF5206e USER’S MANUAL MOTOROLA
• Addresses not assigned to the registers and undefined register bits are reserved for
future expansion. Write accesses to these reserved address spaces and reserved
register bits have no effect; read accesses will return zeros.
• The reset value column indicates the initial value of the register at reset. Certain
registers may be uninitialized upon reset, i.e., they may contain random values after
reset.
• The access column indicates if the corresponding register allows both read/write
functionality (R/W), read-only functionality (R), or write-only functionality (W). If a
read access to a write-only register is attempted, zeros will be returned. If a write
access to a read-only register is attempted the access will be ignored and no write
will occur.
4.4.2 Instruction Cache Register
4.4.2.1 CACHE CONTROL REGISTER (CACR). The CACR controls the operation of
the instruction cache. The CACR provides a set of default memory access attributes used
when a reference address does not map into the spaces defined by the ACRs.
The CACR is a 32-bit write-only supervisor control register. It is accessed in the CPU
address space via the MOVEC instruction with an Rc encoding of $002. The CACR can
be read when in Background Debug mode (BDM). At system reset, the entire register is
cleared.
Table 4-3. Memory Map of I-Cache Registers
ADDRESS NAME WIDTH DESCRIPTION
RESET
VALUE
ACCESS
MOVEC with $002 CACR 32 Cache Control Register $0000 W
MOVEC with $004 ACR0 32 Access Control Register 0 $0000 W
MOVEC with $005 ACR1 32 Access Control Register 1 $0000 W
CENB--CPDICFRZ--CINV--------
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET
:
-----CEIBDCMDBWE--DWP---CLNF1
1514131211109876543210
0000000000000000
RESET
:
0000000000000000
Cache Control Register (CACR)
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eescale S
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