Datasheet

Instruction Cache
MOTOROLA MCF5206e USER’S MANUAL 4-7
CENB - Cache Enable
Generally, longword references are used for sequential fetches. If the processor branches
to an odd word address, a word-sized fetch is generated. The memory array of the
instruction cache is enabled only if CENB is asserted.
0 = Cache disabled
1 = Cache enabled
CPDI - Disable CPUSHL Invalidation
When the privileged CPUSHL instruction is executed, the cache entry defined by bits [8:4]
of the address is invalidated if CPDI = 0. If CPDI = 1, no operation is performed.
0 = Enable invalidation
1 = Disable invalidation
CFRZ - Cache Freeze
This field allows the user to freeze the contents of the cache. When CFRZ is asserted line
fetches can be initiated and loaded into the line-fill buffer, but a valid cache entry can not
be overwritten. If a given cache location is invalid, the contents of the line-fill buffer can be
written into the memory array while CFRZ is asserted.
0 = Normal Operation
1 = Freeze valid cache lines
CINV - Cache Invalidate
Setting this bit forces the cache to invalidate each tag array entry. The invalidation
process requires 32 machine cycles, with a single cache entry cleared per machine cycle.
The state of this bit is always read as a zero. After a hardware reset, the cache must be
invalidated before it is enabled.
0 = No operation
1 = Invalidate all cache locations
CEIB - Cache Enable Noncacheable Instruction Bursting
Setting this bit enables the line-fill buffer to be loaded with burst transfers under control of
CLINF[1:0] for non-cacheable accesses. Noncacheable accesses are never written into
the memory array.
0 = Disable burst fetches on noncacheable accesses
1 = Enable burst fetches on noncacheable accesses
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