Datasheet

TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MOTOROLA MCF5206e USER’S MANUAL xi
Section 6
Bus Operation
6.1 Features ...............................................................................................6-1
6.2 Bus and Control Signals .......................................................................6-1
6.2.1 Address Bus (A[27:0]) ................................................................6-1
6.2.2 Data Bus (D[31:0]) ......................................................................6-2
6.2.3 Transfer Start (TS) .....................................................................6-2
6.2.4 Read/Write (R/W
) .......................................................................6-2
6.2.5 Size (SIZ[1:0]) ............................................................................6-2
6.2.6 Transfer Type (TT[1:0]) ..............................................................6-3
6.2.7 Access Type and Mode (ATM) ...................................................6-3
6.2.8 Asynchronous Transfer Acknowledge (ATA) .............................6-4
6.2.9 Transfer Acknowledge (TA) ........................................................6-4
6.2.10 Transfer Error Acknowledge (TEA) ............................................6-5
6.3 Bus Exceptions .....................................................................................6-5
6.3.1 Double Bus Fault ........................................................................6-5
6.4 Bus Characteristics ..............................................................................6-5
6.5 Data Transfer Mechanism ....................................................................6-6
6.5.1 Bus Sizing ..................................................................................6-7
6.5.2 Bursting Read Transfers: Word, Longword, and Line ..............6-16
6.5.3 Bursting Write Transfers: Word, Longword, and Line ..............6-19
6.5.4 Burst-Inhibited Read Transfer: Word, Longword, and Line ......6-22
6.5.5 Burst-Inhibited Write Transfer: Word, Longword, and Line ......6-26
6.5.6 Asynchronous-Acknowledge Read Transfer ............................6-29
6.5.7 Asynchronous Acknowledge Write Transfer ............................6-32
6.5.8 Bursting Read Transfers with Asynchronous Acknowledge..... 6-34
6.5.9 Bursting Write Transfers with Asynchronous Acknowledge.... 6-37
6.5.10 Burst-Inhibited Read Transfers with Asynch. Acknowledge..... 6-41
6.5.11 Burst-Inhibited Write Transfers with Asynch. Acknowledge..... 6-44
6.5.12 Termination Tied to GND .........................................................6-47
6.6 Misaligned Operands .........................................................................6-48
6.7 Acknowledge Cycles ..........................................................................6-49
6.7.1 Interrupt Acknowledge Cycle ....................................................6-50
6.8 Bus Errors ..........................................................................................6-52
6.9 Bus Arbitration ....................................................................................6-54
6.9.1 Two Master Bus Arbitration Protocol (Two-Wire Mode) ...........6-54
6.9.2 Multiple Bus Master Arbitration Protocol (Three-Wire Mode) ...6-61
6.10 External Bus Master Operation ..........................................................6-67
6.10.1 External Master Read Transfer ............................................... 6-69
6.10.2 External Master Write Transfer ............................................... 6-72
6.10.3 External Master Bursting Read .................................................6-74
6.10.4 External Master Bursting Write .................................................6-77
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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