Datasheet

Bus Operation
6-32 MCF5206e USER’S MANUAL MOTOROLA
Clock 3 (C3)
At the end of C3, the MCF5206e samples the level of internal asynchronous transfer
acknowledge and if it is asserted, latches the current value of D[31:24]. If internal
asynchronous transfer acknowledge is asserted, the byte transfer is complete and the
transfer terminates. If internal asynchronous transfer acknowledge is negated, the
MCF5206e continues to sample internal asynchronous transfer acknowledge and inserts
wait states instead of terminating the transfer. The MCF5206e continues to sample
internal asynchronous transfer acknowledge until it is asserted. As long as ATA is
asserted prior to the falling edge of C2, internal asynchronous transfer acknowledge is
asserted by the rising edge of C3.
6.5.7 Asynchronous Acknowledge Write Transfer
Figure 6-18 is a flowchart for write transfers to 8-, 16-, or 32-bit ports with asynchronous
termination. Bus operations are similar for each case and vary only with the size indicated,
the portion of the data bus used for the transfer, and the specific number of cycles needed
for each transfer.
Figure 6-18. Byte-, Word-, and Longword-Write Transfer with Asynchronous
Termination Flowchart
MCF5206e
SYSTEM
1. DRIVE ADDRESS ON A[27:0]
2. DRIVE R/W
TO WRITE (R/W = 0)
3. DRIVE SIZ[1:0] TO INDICATE BYTE, WORD OR LONGWORD
4. DRIVE TT[1:0] AND ATM TO INDICATE APPROPRIATE
ACCESS TYPE
5. ASSERT TS
FOR ONE CLK CYCLE
1. RECOGNIZE THE TRANSFER IS DONE
2. THREE-STATE D[31:0]
*TO INSERT WAIT STATES, ATA IS DRIVEN NEGATED.
1. DECODE ADDRESS AND SELECT THE APPROPRIATE
SLAVE DEVICE.*
2. ASSERT ATA
3. CAPTURE THE DATA FROM THE APPROPRIATE BYTE
LANES BASED ON SIZ[1:0], A[1:0] AND PORT SIZE
1. NEGATE TS
2. DRIVE ATM TO INDICATE APPROPRIATE ACCESS TYPE
3. DRIVE DATA ON APPROPRIATE BYTE LANES BASED ON
SIZ[1:0], A[1:0] AND PORT SIZE
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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