Datasheet

Bus Operation
MOTOROLA MCF5206e USER’S MANUAL 6-53
Figure 6-32 shows a bursting supervisor code longword-read access from a 16-bit port
with a transfer error.
Figure 6-32. Bursting Longword-Read Access from 16-Bit Port Terminated with TEA
Timing
Clock 1 (C1)
The read cycle starts in C1. During C1, the MCF5206e places valid values on the address
bus (A[27:0]) and transfer control signals. The transfer type (TT[1:0]) signals identify the
specific access type and ATM identifies the transfer as code. The read/write (R/W) signal
is driven high for a read cycle, and the size signals (SIZ[1:0]) are driven to $0 to indicate
a longword transfer. The MCF5206e asserts transfer start (TS) to indicate the beginning
of a bus cycle.
Clock 2 (C2)
During C2, the MCF5206e negates TS, drives ATM high to identify the transfer as
supervisor. The selected device detects an error and asserts TEA. At the end of C2, the
MCF5206e samples the level of TEA.
If it is asserted, the transfer of the longword is
aborted and the transfer terminates.
TS
R/W
CLK
TT[1:0]
ATM
TA
D[31:0]
TEA
SIZ[1:0]
C1 C2
$0
$0
A[27:0]
$ADDR
ATA
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