Datasheet

Bus Operation
6-80 MCF5206e USER’S MANUAL MOTOROLA
Figure 6-48 illustrates TA assertion by the MCF5206e during external master bursting
write transfers.
Figure 6-48. External Master Bursting Longword Write Transfer to a 16-Bit Port
Using MCF5206e Transfer Acknowledge Timing (No Wait States)
Clock 1 (C1)
The write cycle starts in C1. During C1, the external master places valid values on the
address bus (A[27:0]) and transfer control signals. The read/write (R/W
) signal is driven
low for a write cycle, and the size signals (SIZ[1:0]) are driven to $0 to indicate a longword
transfer. The external master asserts TS
to indicate the beginning of a bus cycle.
Clock 2 (C2)
At the start of C2, the MCF5206e registers and decodes the external master address bus,
read/write and size signals. If the external master automatic acknowledge (EMAA) bit in
the Default Memory Control Register (DMCR) is set to 1, the MCF5206e selects the
indicated number of wait states for loading into the internal wait state counter. During C2,
the external master negates TS, drives the appropriate data onto the data bus, and
samples the level of TA
. The selected device(s) decodes the address and if ready, latches
the appropriate data from the data bus.
EM TS
EM A[27:2]
EM R/W
CLK
TA
EM D[31:16]
EM SIZ[1:0]
C1 C2 C3
C4
C5
$ADDR
EM A[1]
$0
EM A[0]
TEA
ATA
Fr
eescale S
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Freescale Semiconductor, Inc.
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