Datasheet

MOTOROLA MCF5206e USER’S MANUAL 9-1
SECTION 9
CHIP SELECT MODULE
9.1 INTRODUCTION
The chip select module provides user-programmable control of the eight chip select and four
write enable outputs. This subsection describes the operation and programming model of
the chip select registers, including the chip select address, mask, and control registers.
9.1.1 Features
The following list summarizes the key chip select features:
• Eight programmable chip selects
• Address masking for memory block sizes from 64 K- to 2 GBytes
• Programmable wait states and port sizes
• Programmable address setup
• Programmable address hold for read and write
• Programmable wait states and port sizes for default memory
• External master access to chip selects
9.2 CHIP SELECT MODULE I/O
9.2.1 Control Signals
The chip select controller outputs eight chip select and four write enables. The chip select
controller activates these signals for ColdFire core-initiated transfers as well as during
external master-initiated transfers. The chip select controller can also output transfer
acknowledge (TA) during external master transfers.
9.2.1.1 CHIP SELECT (CS[7:0]). These active-low output signals provide control for
peripherals and memory. CS
[7:4] are multiplexed with upper address signals (A[27:24]) and
the write enable (WE
[3:0]) signals. CS[0] provides the special function of global chip select
to let you relocate boot ROM at any defined address space. CS[1] provides the special
function of asserting during CPU space accesses including interrupt acknowledge cycles.
9.2.1.2 WRITE ENABLE (WE[3:0]). These active-low output signals provide control for
peripherals and memory during write transfers. WE[3:0] are multiplexed with upper address
and upper chip selects.
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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