Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-9
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
address pins (A[x]) in the following order: A[9] to DA[0], A[10] to DA[1], A[11] to DA[2],
A[12] to DA[3], A[13] to DA[4], A[14] to DA[5], A[15] to DA[6], A[16] to DA[7], and A[17] to
DA[8].
When the ColdFire core initiates a transfer to an address location in the DRAM, the
MCF5206e drives the internal transfer address IA[27:0] onto the MCF5206e address pins
A[27:0] and asserts RAS. This places the internal transfer address bits IA[17:9] into the
DRAM as the row address. Then the MCF5206e internally multiplexes and drive the
internal transfer address bits IA[8:0] onto the MCF5206e address pins A[17:9] and asserts
CAS. This places the internal transfer address bits IA[8:0] into the DRAM as the column
address.
Figure 11-2. Address Multiplexing For 8-bit DRAM With 512 Byte Page Size
The port size (PS) and the bank page size (BPS) determine which address bus pins are
used to drive the row address and column address. Tables 11-6,11-7, and 11-8 show
which internal transfer address bits are driven on each address pin during the assertion of
RAS and during the assertion of CAS for all combinations of port size (PS) and bank page
IA[17]
IA[16]
IA[15]
IA[14]
IA[13]
IA[12]
IA[11]
IA[10]
IA[9]
A[17]
A[16]
A[15]
A[14]
A[13]
A[12]
A[11]
A[10]
A[9]
DA[8]
DA[7]
DA[6]
DA[5]
DA[4]
DA[3]
DA[2]
DA[1]
DA[0]
IA[8]
IA[7]
IA[6]
IA[5]
IA[4]
IA[3]
IA[2]
IA[1]
IA[0]
IA[17]
IA[16]
IA[15]
IA[14]
IA[13]
IA[12]
IA[11]
IA[10]
IA[9]
A[17]
A[16]
A[15]
A[14]
A[13]
A[12]
A[11]
A[10]
A[9]
DA[8]
DA[7]
DA[6]
DA[5]
DA[4]
DA[3]
DA[2]
DA[1]
DA[0]
IA[8]
IA[7]
IA[6]
IA[5]
IA[4]
IA[3]
IA[2]
IA[1]
IA[0]
INTERNAL
TRANSFER
ADDRESS
MCF5206e
ADDRESS
PINS
DRAM
ADDRESS
INPUTS
ROW ADDRESS
GENERATION
COLUMN ADDRESS
GENERATION
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...