Datasheet

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DRAM Controller
11-16 MCF5206e USER’S MANUAL MOTOROLA
is occurring and asserts RAS. The MCF5206e then drives the column address onto the
same address pins and asserts CAS. When the cycle is complete, both RAS and CAS are
negated.
11.3.3.1 NONBURST TRANSFER IN NORMAL MODE. A nonburst transfer to DRAM
occurs when the operand size is the same or smaller than the DRAM port size
(e.g.,longword transfer to a 32-bit port, or byte transfer to a 16-bit port). Nonburst transfers
always start with the assertion of TS.
The start of a transfer to a DRAM bank can be delayed by the DRAMC until the
programmed RAS precharge time is met. A transfer to a different DRAM bank than the
previous transfer is never delayed due to RAS precharge because that bank has already
been precharged.
The timing of nonburst reads and nonburst writes is identical in normal page mode, with
the exception of when the DRAM drives data on reads and when the MCF5206e drives
data on writes.
The fastest possible nonburst transfer in normal mode requires 3 clocks with a 1.5 clock
RAS precharge time. You can program the DCTR to generate slower normal mode
transfers.
Figure 11-5 shows the timing of a back-to-back nonburst byte-read transfer to an 8-bit port
in normal mode.
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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