Datasheet

DRAM Controller
MOTOROLA MCF5206e USER’S MANUAL 11-23
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Clock H3
The internal transfer acknowledge asserts to indicate that the first byte transfer of the word
burst will be completed on the next rising edge of CLK.
Clock H4
The MCF5206e negates the internal transfer acknowledge, and CAS[0] ending the first
byte write transfer of the word burst. At this point, the new page has been opened;
therefore, the MCF5206e continues to assert RAS. The negation of CAS[0] begins the
CAS precharge. The MCF5206e drives the next column address on A[27:9] and the next
data is driven on D[31:24].
Clock L4
The MCF5206e asserts CAS[0] to indicate the column address is valid on A[27:9].
Clock H5
The internal transfer acknowledge asserts to indicate that the first byte transfer of the word
burst will be completed on the next rising edge of CLK.
Clock H6
The MCF5206e negates the internal transfer acknowledge and CAS[0] ending the final
byte write of the word burst. Because the bank is in fast page mode, MCF5206e continues
to assert RAS. The negation of CAS[0] begins the CAS precharge. When the burst write
is completed, the MCF5206e three-states D[31:0].
11.3.4.2 PAGE HIT READ TRANSFER IN FAST PAGE MODE.
A read transfer to an open page results in a page-hit read. The timing of page-hit reads
differs from the timing of page-hit writes (page-hit writes are described in Section 11.3.4.3
Page-Hit Write Transfer in Fast Page Mode). The start of a page-hit read transfer to a
DRAM bank in fast page mode can be delayed by the DRAMC until the programmed CAS
precharge time is reached.
The fastest possible nonburst page-hit read transfer in fast page mode takes 2 clocks with
a 0.5 clock CAS precharge time. The fastest possible burst page-hit read transfer in fast
page mode takes 2 clocks for the initial transfer, and 2 clocks for all secondary reads with
a 0.5 clock CAS
precharge time. You can program the DCTR to generate slower fast page
mode transfers.
Figure 11-8 shows the timing of a nonburst read opening a page and a subsequent page-
hit read being generated. The first transfer that opens the page is a longword read transfer
from a 32-bit port in fast page mode. The first read transfer is followed by a second page-
hit longword read transfer. The timing of a page-hit read transfer is the same regardless
of whether the page was opened by a burst read, burst write, nonburst read, or nonburst
write transfer.
Fr
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Freescale Semiconductor, Inc.
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