Datasheet

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
DRAM Controller
11-34 MCF5206e USER’S MANUAL MOTOROLA
Clock H3
The internal transfer acknowledge asserts to indicate that the first word transfer of the
longword burst will be completed on the next rising edge of CLK.
Clock H4
The MCF5206e negates the internal transfer acknowledge, and CAS[1:0], ending the first
word write transfer of the longword burst. At this point, the new page has been opened;
therefore, the MCF5206e continues to assert RAS. The negation of CAS[1:0] begins the
CAS precharge. The MCF5206e drives the next column address on A[27:9] and the next
data on D[31:16].
Clock L4
The MCF5206e asserts CAS[1:0] to indicate the column address is valid on A[27:9].
Clock H5
The internal transfer acknowledge asserts to indicate that the first word transfer of the
longword burst will be completed on the next rising edge of CLK.
Clock H6
The MCF5206e negates the internal transfer acknowledge, RAS, and CAS[1:0], ending
the final write transfer of the longword burst. Because the bank is in burst page mode,
MCF5206e precharges RAS at the end of the burst. The negation of RAS begins the RAS
precharge. When the burst write is completed, the MCF5206e three-states D[31:0].
Clock H8
Clock H8 is the earliest the next transfer initiated by the ColdFire core can start. Because
this next DRAM cycle is a nonburst word read transfer, it is handled as a normal mode
transfer. During Clock H8, the MCF5206e drives the row address on A[27:9], drives
DRAMW high indicating a DRAM read transfer, drives SIZ[1:0] to $2 indicating a word
transfer, and asserts TS.
Clock L8
The MCF5206e asserts RAS to indicate the row address is valid on A[27:9].
Clock H9
The MCF5206e negates TS
, and drives the column address on A[27:9]
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...