Datasheet

UART Modules
MOTOROLA MCF5206e USER’S MANUAL 12-11
12.3.2.3 FIFO STACK. The FIFO stack is used in the UART receiver buffer logic. The
FIFO stack consists of three receiver holding registers. The receive buffer consists of the
FIFO and a receiver shift register connected to the RxD (refer to Figure 12-4). Data is
assembled in the receiver shift register and loaded into the top empty receiver holding
register position of the FIFO. Thus, data flowing from the receiver to the CPU is quadruple
buffered.
In addition to the data byte, three status bits, parity error (PE), framing error (FE), and
received break (RB) are appended to each data character in the FIFO; overrun error (OE)
is not appended. By programming the error-mode bit (ERR) in the channel's mode register
(UMR1), you can provide status in character or block modes.
The RxRDY bit in the USR is set whenever one or more characters are available to be
read by the CPU. A read of the receiver buffer produces an output of data from the top of
the FIFO stack. After the read cycle, the data at the top of the FIFO stack and its
associated status bits are ‘'popped,'’ and the receiver shift register can add new data at
the bottom of the stack. The FIFO-full status bit (FFULL) is set if all three stack positions
are filled with data. Either the RxRDY or FFULL bit can be selected to cause an interrupt.
In the character mode, status provided in the USR is given on a character-by-character
basis and thus applies only to the character at the top of the FIFO. In the block mode, the
status provided in the USR is the logical OR of all characters coming to the top of the FIFO
stack since the last reset error command. A continuous logical OR function of the
corresponding status bits is produced in the USR as each character reaches the top of the
FIFO stack.
The block mode is useful in applications where the software overhead of checking each
character's error cannot be tolerated. In this mode, entire messages are received and only
one data integrity check is performed at the end of the message. This mode has a data-
reception speed advantage; however, each character is not individually checked for error
conditions by software. If an error occurs within the message, the error is not recognized
until the final check is performed, and no indication exists as to which message character
is at fault.
In either mode, reading the USR does not affect the FIFO. The FIFO is popped only when
the receive buffer is read. The USR should be read prior to reading the receive buffer. If
all three of the FIFO receiver holding registers are full when a new character is received,
the new character is held in the receiver shift register until a FIFO position is available. If
an additional character is received during this state, the contents of the FIFO are not
affected. However, the previous character in the receiver shift register is lost and the OE
bit in the USR is set when the receiver detects the start bit of the new overrunning
character.
To support control flow capability, you can program the receiver to automatically negate
and assert RTS. When in this mode, the receiver automatically negates RTS when a valid
start bit is detected and the FIFO stack is full. When a FIFO position becomes available,
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