Datasheet

UART Modules
12-20 MCF5206e USER’S MANUAL MOTOROLA
1. Program the UART for the automatic-reset mode: UMR2[5]=1
2. Enable the transmitter
3. Assert the transmitter request-to send control: UOP1[0]=1
4. Send the message
5. Disable the transmitter after the TxRDY bit but not the TxEMP bit in the USR
becomes asserted.
The last character will be transmitted and the UOP0[0] bit will be set causing the
transmitter request-to-send control to be negated.
If both the receiver and the transmitter in the same channel are programmed for RTS
control, RTS control is disabled for both because of this incorrect configuration.
1 = If both TxRDY and TXEMP bits in the UART Status Register (USR) are set, there
will be no change on RTS. For TXRTS to be set to 1 in this condition, customers
must set the UART Output Port Set Data Register (UOP1).
0 = The transmitter has no effect on RTS.
TxCTS — Transmitter Clear-to-Send
1 = Enables clear-to-send operation. The transmitter checks the state of the CTS
input each time it is ready to send a character. If CTS is asserted, the character
is transmitted. If CTS is negated, the channel TxD remains in the high state
(mark condition) and the transmission is delayed until CTS is asserted. Changes
in CTS while a character is being transmitted do not affect transmission of that
character.
0 = The CTS has no effect on the transmitter.
SB3–SB0 — Stop-Bit Length Control
These bits select the length of the stop bit appended to the transmitted character as listed
in Table 12-5. Stop-bit lengths of 9/16 to two bits, in increments of 1/16 bit, are
programmable for character lengths of six, seven, and eight bits. For a character length
of five bits, 1-1/16 to two bits are programmable in increments of 1/16 bit. In all cases, the
receiver only checks for a high condition at the center of the first stop-bit position—i.e.,
one bit time after the last data bit or after the parity bit, if parity is enabled.
If an external 1× clock is used for the transmitter, UMR2 bit 3 = 0 selects one stop bit, and
UMR2 bit 3 = 1 selects two stop bits for transmission.
Fr
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Freescale Semiconductor, Inc.
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