Datasheet

M-Bus Module
MOTOROLA MCF5206e USER’S MANUAL 13-5
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immediately switch over to slave-receive mode and stop driving SDA output. In this case,
the transition from master to slave mode does not generate a STOP condition. Meanwhile,
hardware sets a status bit to indicate loss of arbitration.
13.4.7 Clock Synchronization
Because wire-AND logic is performed on SCL line, a high-to-low transition on SCL line
affects all the devices connected on the bus. The devices start counting their low period
when the master drives the SCL line low. Once a device clock has gone low, it holds the SCL
line low until the clock high state is reached. However, the change of low to high in this
device clock may not change the state of the SCL line if another device clock is still within
its low period. Therefore, synchronized clock SCL is held low by the device with the longest
low period. Devices with shorter low periods enter a high wait state during this time (see
Figure 13-3). When all devices concerned have counted off their low period, the
synchronized clock SCL line is released and pulled high. There is then no difference
between the device clocks and the state of the SCL line and all the devices start counting
their high periods. The first device to complete its high period pulls the SCL line low again.
13.4.8 Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave
devices can hold the SCL low after completion of one byte transfer (9 bits). In such cases,
it halts the bus clock and forces the master clock into wait states until the slave releases the
SCL line.
13.4.9 Clock Stretching
Slaves can use the clock synchronization mechanism to slow down the transfer bit rate.
After the master has driven SCL low the slave can drive SCL low for the required period and
Figure 13-3. Synchronized Clock SCL
INTERNAL COUNTER RESET
SCL1
SCL2
SCL
WAIT
START COUNTING HIGH PERIOD
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