Datasheet

Debug Support
15-30 MCF5206e USER’S MANUAL MOTOROLA
Control Registers (DRc), are addressed using a 4-bit value as part of two new BDM
commands (WDREG, RDREG).
These registers are also accessible from the processor’s supervisor programming model
through the execution of the WDEBUG instruction (Figure 15-5 illustrates the debug module
programming model). Thus, the breakpoint hardware within the Debug module can be
accessed by the external development system using the serial interface, or by the operating
system running on the processor core. It is the responsibility of the software to guarantee
that all accesses to these resources are serialized and logically consistent. The hardware
provides a locking mechanism in the CSR to allow the external development system to
disable any attempted writes by the processor to the Breakpoint Registers (setting IPW =1).
15.3.3.1 ADDRESS BREAKPOINT REGISTERS (ABLR, ABHR). The Address
Breakpoint Registers define an upper (ABHR) and a lower (ABLR) boundary for a region in
the operand logical address space of the processor that can be used as part of the trigger.
The ABLR and ABHR values are compared with the ColdFire CPU core address signals, as
defined by the setting of the TDR.
15.3.3.2 ADDRESS ATTRIBUTE BREAKPOINT REGISTER (AATR). The AATR defines
the address attributes and a mask to be matched in the trigger. The AATR value is compared
with the ColdFire CPU core address attribute signals, as defined by the setting of the TDR.
The AATR is accessible in supervisor mode as debug control register $6 using the
WDEBUG instruction and via the BDM port using the WDMREG command. The lower five
bits of the AATR are also used for BDM command definition to define the address space for
memory references as described in subsection 15.3.2.1 Reuse of the Debug Module
Hardware.
RM[15]–Read/Write Mask
This field corresponds to the R-field. Setting this bit causes R to be ignored in address
comparisons.
SZM[14:13]–Size Mask
This field corresponds to the SZ field. Setting a bit in this field causes the corresponding bit
in SZ to be ignored in address comparisons.
TTM[12:11]–Transfer Type Mask
This field corresponds to the TT field. Setting a bit in this field causes the corresponding bit
in TT to be ignored in address comparisons.
TMM[10:8]–Transfer Modifier Mask
This field corresponds to the TM field. Setting a bit in this field causes the corresponding bit
in TM to be ignored in address comparisons.
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RM SZM TTM TMM R SZ TT TM
AATR Bit Definitions
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