Datasheet

Introduction
1-10 MCF5206e USER’S MANUAL MOTOROLA
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The supervisor programming model includes the upper byte of the SR, which contains
operation control information. The Vector Base Register (VBR) contains the upper 12 bits of
the base address of the exception vector table, which is used in exception processing. The
lower 20 bits of the VBR are forced to zero, allowing the vector table to reside on any 1
Mbyte memory boundary.
The Cache Control Register (CACR) controls enabling of the on-chip cache. Two access
control registers (ACR1, ACR0) allow portions of the address space to be mapped as
noncacheable. See subsections 4.3 and 4.4 for details on these registers.
1.3.1.3 MAC REGISTERS SUMMARY. The processor performs all arithmetic using 2’s
complement, but operands can be signed or unsigned. Registers, memory, or instructions
themselves can contain operands. The operand size for each instruction is either explicitly
encoded in the instruction or implicitly defined by the instruction operation. Table1-3
summarizes the MCF5206e data formats.
1.2.1.4 ADDRESSING CAPABILITIES SUMMARY. The MCF5206e processor supports
seven addressing modes. The register indirect addressing modes support postincrement,
predecrement, offset, and indexing, which are particularly useful for handling data structures
common to sophisticated embedded applications and high-level languages. The program
counter indirect mode also has indexing and offset capabilities. This addressing mode is
typically required to support position-independent software. Besides these addressing
modes, the MCF5206e processor provides index scaling features.
An instruction’s addressing mode can specify the value of an operand or a register
containing the operand. It can also specify how to derive the effective address of an operand
in memory. Each addressing mode has an assembler syntax. Some instructions imply the
addressing mode for an operand. These instructions include the appropriate fields for
operands that use only one addressing mode. Table 1-1 summarizes the specific effective
addressing modes of ColdFire processors. Table 1-2 summarizes the MOVE specific
effective addressing modes.
1.2.1.5 INSTRUCTION SET OVERVIEW. The ColdFire instruction set supports high-level
languages and is optimized for those instructions embedded code most commonly
executes. Table 1-3 lists the notational conventions used throughout this manual, unless
otherwise specified. Table 1-4 provides an alphabetized listing of the ColdFire instruction set
opcode, operation, and syntax. The left operand in the syntax is always the source operand
and the right operand is the destination operand. This instruction set is a simplified version
of the M68K instruction set. The removed instructions include BCD, bit field, logical rotate,
decrement and branch, and integer multiply with a 64-bit result. In addition, nine new MAC
instructions have been added.
Table 1-2. MCF5206e Data Formats
OPERAND DATA FORMAT SIZE
Bit 1 bit
Byte 8 bits
Word 16 bits
Longword 32 bits
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