Datasheet

Signal Description
MOTOROLA MCF5206e USER’S MANUAL 2-5
2.3.1 Chip Selects (A[27:24]/ CS[7:4]/ WE[0:3])
These multiplexed pins can serve as the most significant nibble of the address pins, chip-
selects, or as write enables. Programming the Pin Assignment Register (PAR) in the SIM
determines the function of each of these four multiplexed pins. During reset, these pins
are configured to be write enables.
The active-low chip select output signals provide control for peripherals and memory. You
can program each chip select for an address location, with masking capabilities, port size
and burst-capability indication, wait-state generation, and internal/external termination. A
reset disables these chip selects.
2.3.2 Chip Selects (CS[3:0])
These active-low output signals provide control for peripherals and memory. CS[3] and
CS
[2] are functionally equivalent to the upper order chip selects previously described.
However, CS
[1] can also be programmed to assert during CPU space accesses including
interrupt-acknowledge cycles. CS[0] provides a special function as a global chip select
that lets you relocate boot ROM at any defined address space. CS[0] is the only chip
select initialized during reset. Port size and termination (internal vs. external) for CS[0] are
configured by the logic levels on IPL[2]/IRQ[7], IPL[1]/IRQ[4], and IPL[0]/IRQ[1] during
reset.
2.3.3 Byte Write Enables (A[27:24]/ CS[7:4]/ WE[0:3])
These multiplexed pins can serve as the most significant nibble of the address pins, chip-
selects, or as write enables. Programming the Pin Assignment Register (PAR) in the SIM
determines the function of each of these four multiplexed pins. During reset, these pins
are configured to be write enables.
The active-low write enable output signals provide control for peripherals and memory
during write transfers. During write transfers, these outputs indicate which bytes within a
longword transfer are being selected and which bytes of the data bus will be used for the
transfer. WE[0] controls D[31:24], WE[1] controls D[23:16], WE[2] controls D[15:8] and
WE[3] controls D[7:0]. These generated signals provide byte data select signals that are
decoded from the SIZ[1:0] and A[1:0] signals in addition to the programmed port size and
burst capability of the memory being accessed, as shown in Table 2-3.
2.4 INTERRUPT CONTROL SIGNALS
The interrupt signals supply the external interrupt requests or interrupt level to the
MCF5206e. During reset, these pins configure the processor for the number of wait states
and port size for the boot chip select (CS[0]).
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Freescale Semiconductor, Inc.
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