Datasheet

ColdFire Core
MOTOROLA MCF5206e USER’S MANUAL 3-11
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3.5.10 Fault-on-Fault Halt
If a V2 processor encounters any type of fault during the exception processing of another
fault, the processor immediately halts execution with the catastrophic “fault-on-fault”
condition. A reset is required to force the processor to exit this halted state.
3.5.11 Reset Exception
Asserting the reset input signal to the processor causes a reset exception. The reset
exception has the highest priority of any exception; it provides for system initialization and
recovery from catastrophic failure. Reset also aborts any processing in progress when the
reset input is recognized. Processing cannot be recovered.
The reset exception places the processor in the supervisor mode by setting the S bit and
disables tracing by clearing the T bit in the SR. This exception also clears the M bit and sets
the processor’s interrupt priority mask in the SR to the highest level (level 7). Next, the VBR
is initialized to zero ($00000000). The control registers specifying the operation of any
memories (e.g., cache and/or RAM modules) connected directly to the processor are
disabled.
Note
Other implementation-specific supervisor registers are also
affected. Refer to each of the modules in this user’s manual for
details on these registers.
Once the processor is granted the bus and it does not detect any other alternate masters
taking the bus, the core then performs two longword read bus cycles. The first longword at
address 0 is loaded into the stack pointer and the second longword at address 4 is loaded
into the program counter. After the initial instruction is fetched from memory, program
execution begins at the address in the PC. If an access error or address error occurs before
the first instruction is executed, the processor enters the fault-on-fault halted state.
3.6 INSTRUCTION EXECUTION TIMING
This section presents V2 processor instruction execution times in terms of processor core
clock cycles. The number of operand references for each instruction is enclosed in
parentheses following the number of clock cycles. Each timing entry is presented as C(r/w)
where:
• C - number of processor clock cycles, including all applicable operand fetches and
writes, and all internal core cycles required to complete the instruction execution.
• r/w - number of operand reads (r) and writes (w) required by the instruction. An
operation performing a read-modify-write function is denoted as (1/1).
This section includes the assumptions concerning the timing values and the execution time
details.
3.6.1 Timing Assumptions
For the timing data presented in this section, the following assumptions apply:
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