Datasheet

Instruction Cache
4-4 MCF5206e USER’S MANUAL MOTOROLA
These invalidation operations can be initiated from the ColdFire core or the debug
module.
4.3.4 RESET
A hardware reset clears the CACR disabling the instruction cache. The contents of the tag
array are not affected by the reset. Accordingly, the system startup code must explicitly
perform a cache invalidation by setting CACR[24] before the cache can be enabled.
4.3.5 Cache Miss Fetch Algorithm/Line Fills
As discussed in Section 4.2 Instruction Cache Physical Organization, the instruction
cache hardware includes a 16-byte line fill buffer for providing temporary storage for the
last fetched instruction.
With the cache enabled as defined by CACR[31], a cacheable instruction fetch that
misses in both the tag memory and the line-fill buffer generates a external fetch. The size
of the external fetch is determined by the value contained in the 2-bit CLNF field of the
CACR and the miss address. Table 4-1 shows the relationship between the CLNF bits,
the miss address, and the size of the external fetch.
Depending on the runtime characteristics of the application and the memory response
speed, overall performance may be increased by programming the CLNF bits to values
{00, 01}.
For all cases of a line-sized fetch, the critical longword defined by bits [3:2] of the miss
address is accessed first followed by the remaining three longwords that are accessed by
incrementing the longword address in a modulo-16 fashion as shown below:
if miss address[3:2] = 00
fetch sequence = {$0, $4, $8, $C}
if miss address[3:2] = 01
fetch sequence = {$4, $8, $C, $0}
if miss address[3:2] = 10
fetch sequence = {$8, $C, $0, $4}
if miss address[3:2] = 11
fetch sequence = {$C, $0, $4, $8}
Once an external fetch has been initiated and the data loaded into the line-fill buffer, the
instruction cache maintains a special “most-recently-used” indicator that tracks the
Table 4-1. Initial Fetch Offset vs. CLNF Bits
CLNF[1:0]
LONGWORD ADDRESS BITS
00 01 10 11
00 Line Line Line Longword
01 Line Line Longword Longword
1X Line Line Line Line
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