Datasheet

MCF5213 ColdFire Microcontroller, Rev. 3
MCF5213 Family Configurations
Freescale Semiconductor24
1.14 EzPort Signal Descriptions
Table contains a list of EzPort external signals.
Development Serial
Input
DSI Development Serial Input - Internally synchronized input that provides
data input for the serial communication port to the debug module, after
the DSCLK has been seen as high (logic 1).
I
Development Serial
Output
DSO Development Serial Output - Provides serial output communication for
debug module responses. DSO is registered internally. The output is
delayed from the validation of DSCLK high.
O
Debug Data DDATA[3:0] Display captured processor data and breakpoint status. The CLKOUT
signal can be used by the development system to know when to
sample DDATA[3:0].
O
Processor Status Clock PSTCLK Processor Status Clock - Delayed version of the processor clock. Its
rising edge appears in the center of valid PST and DDATA output.
PSTCLK indicates when the development system should sample PST
and DDATA values.
If real-time trace is not used, setting CSR[PCD] keeps PSTCLK, and
PST and DDATA outputs from toggling without disabling triggers.
Non-quiescent operation can be reenabled by clearing CSR[PCD],
although the external development systems must resynchronize with
the PST and DDATA outputs.
PSTCLK starts clocking only when the first non-zero PST value (0xC,
0xD, or 0xF) occurs during system reset exception processing.
O
Processor Status
Outputs
PST[3:0] Indicate core status. Debug mode timing is synchronous with the
processor clock; status is unrelated to the current bus transfer. The
CLKOUT signal can be used by the development system to know
when to sample PST[3:0].
O
All Processor Status
Outputs
ALLPST Logical AND of PST[3:0]. The CLKOUT signal can be used by the
development system to know when to sample ALLPST.
O
Table 17. EzPort Signal Descriptions
Signal Name Abbreviation Function I/O
EzPort Clock EZPCK Shift clock for EzPort transfers. I
EzPort Chip Select EZPCS Chip select for signalling the start and end of
serial transfers.
I
EzPort Serial Data In EZPD EZPD is sampled on the rising edge of
EZPCK.
I
EzPort Serial Data Out EZPQ EZPQ transitions on the falling edge of
EZPCK.
O
Table 16. Debug Support Signals (continued)
Signal Name Abbreviation Function I/O