Datasheet

Electrical Characteristics
MCF5213 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor 33
2.8 General Purpose I/O Timing
GPIO can be configured for certain pins of the QSPI, DDR Control, timer, UART, and Interrupt interfaces. When in GPIO mode,
the timing specification for these pins is given in Table 28 and Figure 5.
The GPIO timing is met under the following load test conditions:
•50pF/50Ω for high drive
•25pF/25Ω for low drive
Frequency un-LOCK range f
UL
–1.5 1.5 % f
ref
Frequency LOCK range f
LCK
–0.75 0.75 % f
ref
CLKOUT period jitter
4, 5, 8 ,9
, measured at f
SYS
Max
• Peak-to-peak (clock edge to clock edge)
• Long term (averaged over 2 ms interval)
C
jitter
—
—
10
.01
% f
sys
On-chip oscillator frequency f
oco
7.84 8.16 MHz
1
All internal registers retain data at 0 Hz.
2
Depending on packaging; see Ta ble 2 .
3
Loss of Reference Frequency is the reference frequency detected internally, which transitions the PLL into self clocked mode.
4
Self clocked mode frequency is the frequency at which the PLL operates when the reference frequency falls below f
LOR
with
default MFD/RFD settings.
5
This parameter is characterized before qualification rather than 100% tested.
6
Proper PC board layout procedures must be followed to achieve specifications.
7
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR).
8
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
sys
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via V
DDPLL
and V
SSPLL
and variation in crystal oscillator frequency increase the C
jitter
percentage
for a given interval.
9
Based on slow system clock of 40 MHz measured at f
sys
max.
Table 28. GPIO Timing
NUM Characteristic Symbol Min Max Unit
G1 CLKOUT High to GPIO Output Valid t
CHPOV
—10ns
G2 CLKOUT High to GPIO Output Invalid t
CHPOI
1.5 — ns
G3 GPIO Input Valid to CLKOUT High t
PVCH
9—ns
G4 CLKOUT High to GPIO Input Invalid t
CHPI
1.5 — ns
Table 27. PLL Electrical Specifications (continued)
(V
DD
and V
DDPLL
= 2.7 to 3.6 V, V
SS
= V
SSPLL
= 0 V)
Characteristic Symbol Min Max Unit